Abstract: Since the inception of hardware emulation, emulators have supported verification of digital designs using 2-state logic. The underlying hardware used for emulation has directly modeled the logic of a design with just 0 and 1 values. This workshop will show how support for 4-state logic improves emulation of digital designs and support for real numbers improves emulation for digital mixed signal designs.
4-state logic emulation has a range of applications. Low power verification controlled with UPF is only partially modeled when constrained to 2-state. Here we’ll present how the corruption, isolation, and propagation of X values in emulation leads to greater verification and simplified debugging. We’ll also look at how introducing the fourth state value Z into emulation improves the verification of multi-driven busses.
All large digital designs must be emulated, but those designs are typically surrounded by analog content for communication to memories, high speed interfaces and RF communication. This analog content is also configured and controlled by processors in the digital design, but the analog content couldn’t be emulated. This workshop will show how adding dedicated floating-point hardware to an emulation processor along with extending the emulation software to understand real number handling and the timing constraints of an analog design extends emulation into the mixed signal domain.
Speakers:
- Brad Budlong, Cadence Design Systems
- Michael Young, Cadence Design Systems