Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. We are composed of a broad range of members that fully support the work of our technical committee to develop technology standards that are balanced, open, and benefit the worldwide electronics industry. Leading companies and semiconductor manufacturers around the world are using our electronic design automation (EDA) and intellectual property (IP) standards in a wide range of projects in numerous application areas to develop consumer, mobile, wireless, automotive, and other “smart” electronic devices. Through an ongoing partnership with the IEEE, standards and technical implementations developed by Accellera Systems Initiative are contributed to the IEEE for formal standardization and ongoing governance.

FPGA Prototyping for Large Multi-Die/ Multi-Core Designs

Thursday, March 7, 2024 11:00 am — 12:30 pm

Today's design size and complexity continue to increase putting greater pressure on meeting compile time and performance goals of the prototype. Together, they are increasing faster than the available compute capability. This has lead to more challenging implementation problems and longer, unpredictable bring-up times for prototypes. To decouple design sizes and compute capacity, a divide-and-conquer approach is needed. This approach helps to enable parallelism.

This workshop will present enhanced capabilities in Synopsys HAPS ProtoCompiler that can enable parallelism - allowing different teams to solve implementation challenges independently and concurrently. In addition, we will discuss how parallelism enables reuse of such implementations for design types involving multi-cores which are often replicated, ultimately reducing peak compute requirements and leading to faster tool execution times. This modular design approach is a framework that will address these needs while also providing a path to faster incremental TaT.