Ping Yeung, Nvidia; Iredamola Olopade, Intel; Kranthi Pamarthi, Renesas Electronics; Chetan Choppali Sudarshan, Marvell Technology; Farhad Ahmed, Siemens EDA; Bill Gascoyne, Blue Pearl; Anupam Bakshi, Agnisys
As complexity and the number of clock domains increase in today’s ASIC designs, we are moving towards a hierarchical verification approach. This tutorial covers the proven clock domain crossings (CDC) and Reset Domain Crossing (RDC) schemes, the verification challenges, and the potential risk mitigation strategies. We will then discuss the hierarchical CDC/RDC verification methodology, the tradeoffs faced when incorporating units from multiple sources, and the challenges when integrating multiple vendor-generated abstracted blocks into an encompassing design. To mitigate these issues, we introduce the Accellera CDC committee, highlight the released CDC standard, and summarize the status of the current efforts.
Topics:
CDC-RDC Basic Knowledge
Clock domain crossing schemes
Reset domain crossing schemes
CDC-RDC Verification
Hierarchical CDC Verification
Accellera CDC Working Group
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. We are composed of a broad range of members that fully support the work of our technical committee to develop technology standards that are balanced, open, and benefit the worldwide electronics industry. Leading companies and semiconductor manufacturers around the world are using our electronic design automation (EDA) and intellectual property (IP) standards in a wide range of projects in numerous application areas to develop consumer, mobile, wireless, automotive, and other “smart” electronic devices. Through an ongoing partnership with the IEEE, standards and technical implementations developed by Accellera Systems Initiative are contributed to the IEEE for formal standardization and ongoing governance.
