Advances in semiconductor process nodes and FinFET transistor design have benefitted System-on-Chip (SoC) technology by allowing more IP to exist on-chip. The increased amount of on-chip IP results in more complex on-chip interconnect requirements to handle the communication between all the IP blocks. Consequently, the interconnect has become a prime source of SoC design challenges in both frontend and backend flows.

Traditional interconnect IP offerings tend to box users into a fixed switch topology, most commonly a cascaded crossbar, forcing SoC teams to design around the interconnect IP’s limitations in ways that magnify challenges rather than solve them. In this tutorial, we will explore how Network-on-Chip (NoC) interconnect IP address the problem of on-chip communication differently than traditional interconnects and enable SoC teams to create a topology that is optimized for their SoC requirements. We will also introduce a framework for how SoC teams can approach NoC topology optimization in their projects.   
Attendees will come away with:

• Differences between NoCs and traditional interconnects

• Tradeoffs between different interconnect topologies

• How to approach finding an optimal interconnect topology for a given set of performance and physical requirements