Technical Session 1 [Functional Coverage Closure]

Tuesday, March 5, 2024

• 1021: Functional Coverage Closure with Python

  9:00 am — 11:00 am • Technical Session

  Seokho Lee, FuriosaAI; Youngsik Kim, FuriosaAI; Suhyung Kim, FuriosaAI; Jeong Ki Lee, FuriosaAI; Wooyoung Choe, FuriosaAI; Minho Kim, FuriosaAI

• 1074: Automated Generation of Interval Properties From Trace-Based Function Models

  9:00 am — 11:00 am • Technical Session

  Robert Kunzelmann, Infineon Technologies AG, Technical University of Munich; Aishwarya Sridhar, Infineon Technologies AG; Daniel Gerl, Infineon Technologies AG, Technical University of Munich; Lakshmi Vidhath Boga, Infineon Technologies AG; Wolfgang Ecker, Infineon Technologies AG, Technical University of Munich

• 1062: Tackling Missing Bins: Refining Functional Coverage In Systemverilog For Deterministic Coverage Closure

  9:00 am — 11:00 am • Technical Session

  Jikjoo Lee, Samsung Electronics, Memory Division South Korea; Kihyun Park, Samsung Electronics, Memory Division South Korea; Tony Gladvin George, Samsung Electronics, Memory Division South Korea; Dongkun An, Samsung Electronics, Memory Division South Korea; Wooseong Cheong, Samsung Electronics, Memory Division South Korea; Byungchul Yoo, Samsung Electronics, Memory Division South Korea

• 1090: mL: Shrinking the Verification volume using Machine Learning

  9:00 am — 11:00 am • Technical Session

  Yash Phogat, Arm Inc.; Patrick Hamilton, Arm Inc.

Technical Session 2 [AI & ML in Verification]

Tuesday, March 5, 2024

• 1044: Requirements Recognition for Verification IP Design Using Large Language Models

  9:00 am — 11:00 am • Technical Session

  Siarhei Zalivaka, Solidigm

• 1083: All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification

  9:00 am — 11:00 am • Technical Session

  Aman Kumar, Infineon Technologies; Deepak Narayan Gadde, Infineon Technologies; Thomas Nalapat, Infineon Technologies; Evgenii Rezunov, Infineon Technologies; Fabio Cappellini, Infineon Technologies

• 1104: Efficient Application Of AI Algorithms for Large-Scale Verification Environments Based on NoC Architecture

  9:00 am — 11:00 am • Technical Session

  Olivera Stojanovic, Vtool; Nemanja Mitrovic, Vtool; Anna Revitzki, Vtool

• 1135: Large Language Model for Verification: A Review and its Application in Data Augmentation

  9:00 am — 11:00 am • Technical Session

  Dan Yu, Siemens EDA; Harry Foster, Siemens EDA; Eman El Mandouh, Siemens EDA; Waseem Raslan, Siemens EDA; Tom Fitzpatrick, Siemens EDA

Technical Session 3 [Formal Verification Use Cases]

Tuesday, March 5, 2024

• 1025: Automating the Formal Verification of Firmware: A Novel Foundation and Scalable Methodology

  9:00 am — 11:00 am • Technical Session

  Bryan Olmos, Infineon Technologies AG; Sanjana Sainath, Infineon Technologies AG; Wolfgang Kunz, Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau; Djones Lettnin, Infineon Technologies AG

• 1027: Automated Formal Verification of a Highly-Configurable Register Generator

  9:00 am — 11:00 am • Technical Session

  Shuhang Zhang, Infineon Technologies AG; Bryan Olmos, Infineon Technologies AG; Basavaraj Naik, Infineon Technologies AG

• 1101: Formal Verification Approach To Verifying Stream Decoders: Methodology & Findings

  9:00 am — 11:00 am • Technical Session

  Abhishek Asi, Intel; Anshul Jain, Intel; Virginia Bao, Intel

• 1138: New Innovative Way To Verify Packaging Connectivity

  9:00 am — 11:00 am • Technical Session

  Mike Walsh, Siemens EDA; Jin Hou, Siemens EDA

Technical Session 4 [UVM Testbenches]

Tuesday, March 5, 2024

• 1031: Leveraging Model Based Verification For Automotive SoC

  3:00 pm — 5:00 pm • Technical Session

  Aswini Kumar Tata, ALLEGRO MICROSYSTEMS LLC; Bhanu Singh, MathWorks; Sanjay Chatterjee, ALLEGRO MICROSYSTEMS LLC; Eric Cigan, MathWorks; Surekha Kollepara, ALLEGRO MICROSYSTEMS LLC; Kamel Belhous, Allegro Microsystems

• 1047: A UVM Multi-Agent Verification IP Architecture to Enable Next-Gen Protocols With Enhanced Reusability, Controllability and Observability

  3:00 pm — 5:00 pm • Technical Session

  Prathik R, Samsung Semiconductor India Research, Bengaluru; Ramesh Madatha, Samsung Semiconductor India Research, Bengaluru; Girish Kumar Gupta, Samsung Semiconductor India Research, Bengaluru; Tony Gladvin George, Samsung Electronics, Korea

• 1103: Leveraging Interface Classes to Improve UVM TLM

  3:00 pm — 5:00 pm • Technical Session

  Neha Goyal, Nvidia Corp.; Justin Refice, Nvidia Corp.

• 1116: Without Objection - Touring The UVM_Objection Implementation - Uses and Improvements

  3:00 pm — 5:00 pm • Technical Session

  Rich Edelman, Siemens EDA

Technical Session 5 [Functional Safety and Verification]

Tuesday, March 5, 2024

• 1022: Leveraging Several Functional Safety Methodologies (Full Faults and SRF) to Enhance Design Quality in Automotive IC

  3:00 pm — 5:00 pm • Technical Session

  Sougata Bhattacharjee, Samsung Semiconductor India Research (SSIR); Gulshan Kumar Sharma, Samsung Semiconductor India Research (SSIR); Wonil Cho, Samsung Electronics; Akshaya Kumar Jain, Samsung Semiconductor India Research (SSIR); James Kim, Siemens; Andrey Likhopoy, Samsung Electronics; Sangkyu Park, Samsung Electronics; Hyeonuk Noh, Samsung Electronics; Ann Keffer, Siemens; Arun Gogineni, Siemens

• 1040: Functional Safety Workflow of Internal IP (NPU) Within Large Automotive IC Through Analysis and Emulation Usage for SW-Based Safety Mechanisms

  3:00 pm — 5:00 pm • Technical Session

  Andrey Likhopoy, Samsung Electronics; Sangkyu Park, Samsung Electronics; Hyeonuk Noh, Samsung Electronics; Wonil Cho, Samsung Electronics; Inhwan Kim, Siemens EDA; Robert Serphillips, Siemens EDA; Chanjin Kim, Siemens EDA; Justin Lee, Siemens EDA; James Kim, Siemens EDA; Sougata Bhattacharjee, Samsung Semiconductor India Research (SSIR); Gulshan Kumar Sharma, Samsung Semiconductor India Research (SSIR); Akshaya Kumar Jain, Samsung Semiconductor India Research (SSIR)

• 1052: AI Based Media Functional Safety and Reliability Verification in Safety-Critical Autonomous Systems

  3:00 pm — 5:00 pm • Technical Session

  Suresh Vasu, Intel Corporation; Palanivel Guruvareddiar, Intel Corporation; Pooja Sundar, Intel Corporation

• 1068: Are My Fault Campaigns Providing Accurate Results for ISO 26262 Certification?

  3:00 pm — 5:00 pm • Technical Session

  James(JAE YUN) Kim, Siemens EDA; Arun Gogineni, Siemens EDA; Ann Keffer, Siemens EDA; Ahn Hyunsun, Samsung LSI

Technical Session 6 [RISCV Design & Verification]

Tuesday, March 5, 2024

• 1008: Crafting A Million Instructions/Sec RISCV-DV -- HPC Techniques to Boost UVM Testbench Performance by over 100X

  3:00 pm — 5:00 pm • Technical Session

  Puneet Goel, Incore Semiconductors; Ritu Goel, Coverify Systems Technology; Jyoti Dahiya, Coverify Systems Technology

• 1081: RISC-V Testing – Status and Current State of the Art

  3:00 pm — 5:00 pm • Technical Session

  Jon Taylor, Imperas Software

• 1055: Unleashing the Power of Whisper for Block-Level Verification in High Performance RISC-V CPU

  3:00 pm — 5:00 pm • Technical Session

  Chenhui Huang, Tenstorrent Inc.; Yu Sun, Tenstorrent Inc.; Joe Rahmeh, Tenstorrent Inc.

• 1136: Extending The RISC-V Verification Interface for Debug Module Co-Simulation

  3:00 pm — 5:00 pm • Technical Session

  Aimee Sutton, Imperas Software Ltd.

Tuesday, March 5, 2024

• 1019: RTL Transformation Methods to Achieve Order of Magnitude TAT Improvement in VLSI Design

  11:00 am — 12:30 pm • Poster Session

  Ashfaq Khan, Intel Corporation; Shuhui Lin, Intel Corporation; Daniel Standring, Intel Corporation; Adam Campos, Intel Corporation; Satish Venkatesan, Intel Corporation; Soowan Suh, Intel Corporation

• 1020: Arithmetic Overflow Verification using Formal LINT Tools

  11:00 am — 12:30 pm • Poster Session

  Kaiwen Chin, Renesas; Esra Sahin, Renesas; Kranthi Pamarthi, Renesas

• 1024: Innovative 4-State Logic Emulation for Power-aware Verification

  11:00 am — 12:30 pm • Poster Session

  Kyoungmin Park, Samsung Electronics; Brad Budlong, Cadence Design Systems; Hyundon Kim, Samsung Electronics; Danny Yi, Cadence Design Systems; Gibs Lee, Cadence Design Systems; Jaehunn Lee, Samsung Electronics; Chulmin Kim, Samsung Electronics; Jaemin Choi, Samsung Electronics; Kijung Yoo, Samsung Electronics; Youngsik Kim, Samsung Electronics; Yogesh Goel, Cadence Design Systems; Seonil Brian Choi, Samsung Electronics

• 1029: A Statistical and Model-Driven Approach for Comprehensive Fault Propagation Analysis of RISC-V Variants

  11:00 am — 12:30 pm • Poster Session

  Endri Kaja, Infineon Technologies AG; Nicolas Gerlin, Infineon Technologies AG; Ungsang Yun, Infineon Technologies AG; Jad Al Halabi, Infineon Technologies AG; Sebastian Prebeck, Infineon Technologies AG; Dominik Stoffel, Rheinland-Pfälzische Technische Universität; Wolfgang Kunz, Rheinland-Pfälzische Technische Universität; Wolfgang Ecker, Infineon Technologies AG

• 1054: The beginning of new norm: CDC/RDC constraints signoff through functional simulation

  11:00 am — 12:30 pm • Poster Session

  Suhas D S, Intel; Ponsankar Arumugam, Intel; Deepmala Sachan, Intel; Ritesh Jain, Intel

• 1061: Metric Driven Microcode Verification: Navigating Microcode Coverage Complexities

  11:00 am — 12:30 pm • Poster Session

  Seungyeon Yu, Samsung Electronics, Memory Division; Damin Son, Samsung Electronics, Memory Division

• 1065: Shift Left on Timing Constraints Verification: Beyond Typical Front-End Execution

  11:00 am — 12:30 pm • Poster Session

  Vineeth B, Intel Technology India Pvt Ltd; Deepmala Sachan, Intel Technology India Pvt Ltd; Ritesh Jain, Intel Technology India Pvt Ltd

• 1088: On Analysis of RDC issues for identifying Reset tree design bugs and further strategies for Noise Reduction

  11:00 am — 12:30 pm • Poster Session

  Farhad Ahmed, Siemens EDA; Manish Bhati, Siemens EDA; Lyle Benson, Siemens EDA

• 1102: Interoperability Validation Without Direct Integration

  11:00 am — 12:30 pm • Poster Session

  Nicholas Nuti, Intel Corporation; Srinivasan Jambulingam, Intel Corporation

• 1117: AI-based Algorithms to Analyze and Optimize Performance Verification Efforts

  11:00 am — 12:30 pm • Poster Session

  Sharada Vajja, Google LLC; Raghu Alamuri, Google LLC; Saksham Mehra, Google LLC

• 1124: Achieving End-to-End Formal Verification of Large Floating-Point Dot Product Accumulate Systolic Units

  11:00 am — 12:30 pm • Poster Session

  Emiliano Morini, Intel; Bill Zorn, Intel; Disha Puri, Intel; Madhurima Eranki, Intel; Shravya Jampana, Intel

• 1131: Towards Efficient Design Verification – Constrained Random Verification using PyUVM

  11:00 am — 12:30 pm • Poster Session

  Deepak Narayan Gadde, Infineon Technologies; Suruchi Kumari, Infineon Technologies; Aman Kumar, Infineon Technologies

• 1140: Enabling True System-Level, Mixed-Signal Emulation

  11:00 am — 12:30 pm • Poster Session

  Nimay Shah, Analog Devices Inc.; Pranav Dhayagude, Analog Devices Inc.; Paul Wright, Analog Devices Inc.; Raj Mitra, Cadence Design Systems Inc.

• 1141: A UVM SystemVerilog Testbench for Directed and Random Testing of an AMS Low-Dropout Voltage Regulator

  11:00 am — 12:30 pm • Poster Session

  Charles Dancak, Betasoft Inc.

• 1145: Scalable Functional Verification using Portable Stimulus Standard

  11:00 am — 12:30 pm • Poster Session

  Santosh Kumar, Qualcomm Technologies Inc; Yogish Raja, Qualcomm Technologies Inc; Geetika Agrawal, Qualcomm Technologies Inc; Karthikeyan Sugumaran, Qualcomm Technologies Inc; Arjun Vazhayil, Qualcomm Technologies Inc; Tommy Brunansky, Qualcomm Technologies Inc.

• 1063: Synthetic Traffic based SOC Performance Verification Methodology