Technical Sessions 2024

Session 1 [Functional Coverage Closure]

[1021] Functional Coverage Closure with Python
[1074] Automated Generation of Interval Properties From Trace-Based Function Models
[1061] Metric Driven Microcode Verification: Navigating Microcode Coverage Complexities
[1062] Tackling Missing Bins: Refining Functional Coverage in SystemVerilog for Deterministic Coverage Closure

Session 2 [AI & ML in Verification]

[1044] Requirements Recognition for Verification IP Design Using Large Language Models
[1083] ReFormAI: A Formal Verified Dataset for Assessment of CWEs in Generative AI Hardware Designs
[1104] Efficient application of AI algorithms for large-scale verification environments based on NoC architecture
[1135] Large Language Model for Verification: A Review and Its Application in Data Augmentation

Session 3 [Formal Verification Use Cases]

[1025] Automating the Formal Verification of Firmware: A Novel Foundation and Scalable Methodology
[1027] Automated Formal Verification of a Highly-Configurable Register Generator
[1101] Formal Verification Approach to Verifying Stream Decoders: Methodology & Findings
[1138] New Innovative Way to Verify Packaging Connectivity

Session 4 [UVM Testbenches]

[1031] Leveraging Model Based Verification for Automotive SoC
[1047] A UVM Multi-Agent Verification IP architecture to enable Next-Gen protocols with enhanced reusability, controllability and observability
[1103] Leveraging Interface Classes to Improve UVM TLM
[1116] Without Objection - Touring the uvm_objection implementation - uses and improvements

Session 5 [Functional Safety and Verification]

[1022] Leveraging Several Functional Safety Methodologies (Full Faults and SRF) to Enhance Design Quality in Automotive IC
[1029] A Statistical and Model-Driven Approach for Comprehensive Fault Propagation Analysis of RISC-V Variants
[1040] Functional Safety Workflow of Internal IP (NPU) Within Large Automotive IC Through Analysis and Emulation Usage for SW-based Safety Mechanisms
[1052] AI based Media Functional safety and Reliability verification in Safety-Critical Autonomous Systems

Session 6 [RISCV Design & Verification]

[1008] Crafting a Million Instr/Sec RISCV-DV -- HPC Techniques to Boost UVM Testbench Performance by over 100x
[1081] RISC-V Testing – status and current state of the art
[1055] Unleashing the Power of Whisper for block-level verification in high performance RISC-V CPU
[1136] Extending the RISC-V Verification Interface for Debug Module Co-simulation

Session 7 [Regression Management Techniques]

[1078] Bus Trace System: Automated Bus Traffic Debugging in IP-XACT Based SoC Beyond Traditional Debugging Methods
[1095] Functional Verification from Chaos to Order: Using Continuous Integration for Hardware Functional Verification
[1099] Novel Method To Speed-Up UVM Testbench Development

Session 8 [Mixed Signal with UVM Verification]

[1112] Advanced UVM Based Chip Verification Methodologies with Full Analog Functionality
[1137] UVM Testbench Automation for AMS Designs
[1160] DV UVM based AMS co-simulation and verification methodology for mixed signal designs

Session 9 [SystemVerilog Verification Techniques]

Session 10 [Requirements Definition and Traceability]

[1002] PyRDV: a Python-based solution to the requirements traceability problem
[1009] Verification Plan in Requirements Management Tool: Simple Traceability and Automated Interface to Regression Manager
[1133] Gherkin Implementation in SystemVerilog Brings Agile Behavior-Driven Development to UVM

Session 11 [Formal: Liveness and Use Cases]

[1016] Forward Progress checks in Formal Verification: Liveness vs Safety
[1114] Liveness Assume-Guarantee Proof Schema: A step towards Liveness Full Proofs
[1036] Next-Generation Formal Property Verification: Lightweight Theorem Proving Integrated into Model Checking

Session 12 [Analog Modeling in SystemVerilog]

[1049] Functional Verification of Analog Devices modeled using SV-RNM
[1091] Variation-aware modeling method for MRAM behavior model using System-Verilog
[1156] SV_LUT: A SystemVerilog Look Up Table package for developing complex AMS Real Number Modeling

[1019] RTL Transformation Methods to Achieve Order of Magnitude TAT Improvement in VLSI Design
[1020] Arithmetic Overflow Verification using Formal LINT Tools
[1024] Innovative 4-State Logic Emulation for Power-aware Verification
[1054] The beginning of new norm: CDC/RDC constraints signoff through functional simulation
[1063] Synthetic Traffic based SOC Performance Verification Methodology
[1065] Shift Left on Timing Constraints Verification: Beyond Typical Front-End Execution
[1068] Are My Fault Campaigns Providing Accurate Results for Iso 26262 Certification?
[1070] CXL verification using Portable Stimulus
[1088] On Analysis of RDC issues for identifying Reset tree design bugs and further strategies for Noise Reduction
[1090] mL: Shrinking the Verification volume using Machine Learning
[1102] Interoperability Validation Without Direct Integration
[1117] AI-based Algorithms to Analyze and Optimize Performance Verification Efforts
[1124] Achieving End-to-End Formal Verification of Large Floating-Point Dot Product Accumulate Systolic Units
[1131] Towards Efficient Design Verification – Constrained Random Verification using PyUVM
[1140] Enabling True System-Level, Mixed-Signal Emulation
[1141] A UVM SystemVerilog Testbench for Directed and Random Testing of an AMS Low-Dropout Voltage Regulator
[1145] Scalable Functional Verification using Portable Stimulus Standard
[1161] Complexities & Challenges of UPF Corruption Model in Low Power Emulation