Session Chair: Progyna Khondkar

  • [1082] Refinable Macros and Terminal Boundaries in UPF 4.0: Empowering Soft IPs of the Future 

    • Amit Srivastava, Synopsys Inc; John Decker, Cadence Design Systems; Lakshmanan Balasubramanian, IEEE & ACM

  • [1127] Applications for UPF HDL Supply Tunneling in Mixed Signal Design 

    • Daniel Cross, Cadence Design Systems

  • [1136] Future Proofing Power Intent Specification through Unified Power Format 4.0 for Evolving Advanced State Retention Strategies 

    • Lakshmanan Balasubramanian, IEEE, ACM & Texas Instruments (India) Pvt. Ltd.; Amit Srivastava, Synopsys Inc.; Raguvaran Easwaran, Intel India Pvt. Ltd.; John Decker, Cadence Design Systems; Rick Koster, SIEMENS EDA; Progyna Khondkar, Cadence Design Systems; Paul Bailey, Nordic Seminconductors; Barry Pangrle, Abacus Semiconductor Corporation; Shreedhar Ramachandra, Synopsys Inc.; Phil Giangarra, Cadence Design Systems; John Biggs, IEEE; David Cheng, Cadence Design Systems

  • [1034] What’s New in IEEE 1801 and Why you Need to Know Now? 

    • Progyna Khonkdar, Cadence Design Systems

Session Chair: Ann Keffer

  • [1062] Lessons Learned Using Formal  for Functional Safety 

    • Doug Smith, Doulos

  • [1072] A Comprehensive Safety Verification Solution for SEooC Automotive SoC 

    • Gaurav Kumar Yadav, Samsung Semiconductor India R&D; Debasis Mishra, Samsung Semiconductor India R&D; PrashantKumar Shukranath Sonavane, Samsung Semiconductor India R&D; Aniruddha N Anavatti, Samsung Semiconductor India R&D; Pattan Farooq Khan, Samsung Semiconductor India R&D; Garima Srivastava, Samsung Semiconductor India R&D       

  • [1140] A Novel Approach for faster diagnostic coverage closure aided by STL of CPU Cores 

    • Naveen Srivastava, Samsung Semiconductor India R & D; Amresh Kumar Lenka, Samsung Semicoductor India R&D; Varun Kumar C, Samsung Semiconductor India R & D; Subramanian R, Samsung Semiconductor India R & D; Sekhar Dangudubiyyam, Samsung Semiconductor India R & D        

  • [1055] Automated Formal Verification of Area-Optimized Safety Registers in Automotive SoCs 

    • Shuhang Zhang, Infineon Technologies AG; Bryan Olmos, Infineon Technologies AG

Session Chair: Paul Marriott

  • [1005] Bridging the Verification Gap in DSP Designs A Case Study on LMS Adaptive Filter Datapath Cycle-Accurate Verification Using Generative AI and MATLAB DPIGEN 

    • Kuan-Ting Chen, Silicon Labs

  • [1016] Towards Automated Verification IP Instantiation via LLMs 

    • Ghaith Bany Hamad, Nvidia; Michael Marcotte, Nvidia; Syed Suhaib, Nvidia          

  • [1048] Saarthi: The First AI Formal Verification Engineer 

    • Aman Kumar, Infineon Technologies; Deepak Narayan Gadde, Infineon Technologies; Keerthan Kopparam Radhakrishna, Infineon Technologies; Djones Lettnin, Infineon Technologies         

  • [1030] An Early Stage Coverage Measurement Methodology For Common Features Of System-On-Chip Verification, Using Design Metadata And Large Language Models 

    • Myeongwhan Hyun, Samsung Electronics; Jaehyeok Lee, Samsung Electronics; Jin Choi, Samsung Electronics; Dongjoo Kim, Samsung Electronics; Seonghee Yim, Samsung Electronics; Youngsik Kim, Samsung Electronics; Seonil Brian Choi, Samsung Electronics  

  • [1004] A Survey of Predictor Implementation using High-Level Language Co-simulation 

    • Sean Little, Verus Research

  • [1008] Automating Datapath Verification and Bug Correction via Equality Saturation 

    • Emiliano Morini, Intel Corporation; Samuel Coward, Intel Corporation; Theo Drane, Intel Corporation; Rafael Barbalho, Intel Corporation; George Constantinides, Imperial College London        

  • [1027] Technical Documents Version Management System Based on Large Language Models 

    • Siarhei Zalivaka, SK Hynix

  • [1028] Continuous Integration in SoC Design:  Challenges and Solutions 

    • Wei Liu, sudoinfotech; Jianjun Li, sudoinfotech; Liangfeng Yang, sudoinfotech; Liang Li, sudoinfotech         

  • [1031] Enhancing SDC Verification in SoCs: Heatmap Visualization and Machine Learning Approaches for Optimal Coverage Closure 

    • Seungkyu Baek, Samsung Electronics; Jaein Hong, Samsung Electronics; Moonki Jun, Samsung Electronics; Sungcheol Park, Samsung Electronics         

  • [1033] A Hybrid Verification Approach for Cache Coherent Systems: Functionality and Performance 

    • Jiang-Tang XIao, Mediatek; Yung-Cheng Chen, Cadence; Harish Peta, Cadence; Osmond Yao, Mediatek         

  • [1035] An Effective Digital Logic Verification Methodology of High-Speed Interface IP Using a Configurable AFE Behavioral and C hannel Model 

    • Kiyoon Shim, Samsung electronics; Beomseok Kang, Samsung electronics; Seungsik Eom, Samsung electronics

  • [1036] Breaking the Formal Verification Bottleneck: Faster and More Comprehensive Testing of Parameterized Modules 

    • Menachem Rappaport, Veriest; Ariel Ansbacher, Veriest; Elchanan Rappaport, Veriest          

  • [1039] Time-travel Debugging for High-level Synthesis Code 

    • Jonathan Bonsor-Matthews, LightBlue Logic Limited; Greg Law, Undo Limited           

  • [1046] Static Structural Analysis and Formal Verification of SoC with Software Safety Mechanisms for Functional Safety 

    • Hyunsun Ahn, Samsung Electronics Co., Ltd.; Euisang Yoon, SIEMENS EDA; Namyul Cho, SIEMENS EDA; Arun Gogineni, SIEMENS EDA; Ann Keffer, SIEMENS EDA; Sungjin Park, SIEMENS EDA; Sungyun Yoo, SIEMENS EDA; Bumju Kim, Samsung Electronics Co., Ltd.; Junhyuk Park, Samsung Electronics Co., Ltd.; Youngsik Kim, Samsung Electronics Co., Ltd.; Seonil Brian Choi, Samsung Electronics Co., Ltd.  

  • [1069] Robust Verification of Clock Tree Network  using “Clock Monitor” Integrated by ACRMG 

    • Tejas Dipakkumar Dalal, Samsung Semiconductor India Research; Giridhar S, Samsung Semiconductor India Research; Jeevan Nataraju, Samsung Semiconductor India Research; Garima Srivastava, Samsung Semiconductor India Research         

  • [1078] Real-time synchronization of C model with UVM Testbench 

    • Kirtan Mehta, onsemi

  • [1084] Reset Sweep Verification for Elimination of Reset Domain Crossing Blind Spots in Design 

    • Nitika Gupta, NXP Semiconductors; Neha Srivastava, NXP Semiconductors; Vivek Yadav, NXP Semiconductors 

  • [1089] Register Access by Intent: Towards Generative RAL based Algorithms 

    • Ahmed Allam, ICpedia

  • [1098] Achieving Full Liveness Proofs via a Systematic Assume-Guarantee Approach and Iterative Helper Generation

    • Stella Simic, Qualcomm; Karthik Baddam, Qualcomm           

  • [1104] Formal and Simulation Methods Unite to Rescue the Damsel in Distress—Unclassified Faults 

    • Siri Rajanedi, Analog Devices India pvt ltd; Prashantkumar Ravindra, Analog Devices India pvt ltd           

  • [1112] Traversing the Abyss : Formal exploration of intricate state space 

    • Sakthivel Ramaiah, Cadence Design System; Tanishq Sharma, Cadence Design System; Craig Deaton, Cadence Design System          

  • [1134] Sleipnir: Bringing constraints and randomization to software defined data types 

    • Nikhil Soraba, Microsoft; Leon Cao, Microsoft 

 Session Chair: Santosh Kumar

  • [1123] PSS and Protocol VIP: Like a Hand in a Glove 

    • Bob Oden, Siemens EDA; Tom Fitzpatrick, Siemens EDA

  • [1085] Accelerating Device Sign-off through a Unified Environment for Design Verification, Silicon Validation and ATE with PSS 

    • Maximilian Suckert, Advantest Europe GmbH; Sergey Khaikin, Cadence Design Systems, Inc.; Arjun Ashok Vazhayil, Qualcomm Technologies, Inc.; Nandeep Devendra, Qualcomm Technologies, Inc.; Abhijeet Samudra, Advantest America, Inc.; Klaus-Dieter Hilliges, Advantest Europe GmbH; Moshik Rubin, Cadence Design Systems  

  • [1051] Performance verification for AI Heterogenous Multicore Systems using Portable Stimuli Standard 

    • Pietro Locci, Synopsys; Hillel Miller, Synopsys           

  • [1040] What Just Happened? Behavioral Coverage Tracking in PSS 

    • Tom Fitzpatrick, Siemens EDA; Wael Mahmoud, Siemens EDA; Mohamed Nafea, Siemens EDA

 Session Chair: Kamel Belhous

  • [1019] AFCML: Accelerating the Functional Coverage through Machine Learning within a UVM Framework 

    • Syed Jawad Shah, National University of Science & Technology (NUST), Islamabad; Majeed Ahmed, National University of Science & Technology (NUST), Islamabad; Muhammad Imran, National University of Science & Technology (NUST), Islamabad; Haroon Waris, National University of Science & Technology (NUST), Islamabad; Nasir Mohyuddin, National University of Science & Technology (NUST), Islamabad; Muhammad Mahboob Ur Rehman, DreamBig Semiconductor       

  • [1022] Reaching 100% Functional Coverage Using Machine Learning: A Journey of Persistent Efforts 

    • Jaecheon Kim, Samsung Electronics Co., Ltd.; Taewook Nam, Samsung Electronics Co., Ltd.; Wonil Cho, Samsung Electronics Co., Ltd.

  • [1063] Stimulus Diversification and Coverage Closure of 3D NAND Flash with Artificial Intelligence 

    • Goutham Pallela, Micron Technology, Inc.; Peiyao Shi, Micron Technology, Inc.; Srinivas Deshmukh, Micron Technology, Inc.; Rohit Suvarna, VerifAI Inc.; Sandeep Srinivasan, VerifAI Inc.; Bill Hughes, VerifAI Inc.; Vaishnavi Venkatesh, Micron Technology, Inc.      

  • [1096] Functional Coverage Closure in SoC Interconnect Verification with Iterative Machine Learning 

    • Jihye Kwon, Cadence Design Systems; Sukwon Ha, Samsung Electronics Co., Ltd.; Youngsik Kim, Samsung Electronics Co., Ltd.; Seonil Choi, Samsung Electronics Co., Ltd.; Daeseo Cha, Samsung Electronics Co., Ltd.; Space Kim, Samsung Electronics Co., Ltd.; Kunhyuk Kang, Samsung Electronics Co., Ltd.; John Pierce, Cadence Design Systems; Amit Metodi, Cadence Design Systems; Saurabh Sharma, Cadence Design Systems; Heedo Jung, Cadence Design Systems; Yosinori Watanabe, Cadence Design Systems 

 Session Chair: Harish Patel

  • [1065] A Scalable Gray-Box Instance-Based Reachability Predictor for Automated DV Regression Scheduling 

    • Lorenzo Ferretti, Micron Technology; Chinmaya Behera, Micron Technology; Surya Teja Bandlamudi, Micron Technology; Nihar Athreyas, Micron Technology; Vikram Narayan, Micron Technology; Samir Mittal, Micron Technology       

  • [1045] A Large Language Model-Based Framework for Enhancing Integrated Regression 

    • Jin Choi, Samsung Electronics; Noh Sangwoo, Samsung Electronics           

  • [1058] Automating Regression Triage in Design Verification Using AI-Based Random Forest Models 

    • Lingkai Shi, AMD; Rohit Mathur, Amd           

  • [1132] A Novel AI-ML Regression Flow for SoC verification 

    • Sunil Shrirangrao Kashide, samsung semiconductor India(SSIR); Narasimha Rao Chinni, samsung semiconductor India(SSIR); Garima Srivastava, samsung semiconductor India(SSIR)        

 Session Chair: Vibarajan Viswanathan

  • [1054] Automatic Test Pattern Generation Using Formal Verification and Fault Injection Methods 

    • Jad Al Halabi, Infineon Technologies AG; Endri Kaja, Infineon Technologies AG; Ecker Wolfgang, Infineon Technologies AG          

  • [1025] Hierarchical Formal Verification and Progress Checking of Network-On-Chip Design 

    • Pritam Roy, NVIDIA; Ping Yeung, NVIDIA; Joon Hong, NVIDIA; Abhishek Desai, NVIDIA; Aishwarya Raj, NVIDIA; Chirag Agarwal, NVIDIA; Dhruvin Patel, NVIDIA      

  • [1080] End-to-end Framework for Novel Datatype Arithmetic Verification 

    • Qiuwen Lou, Amazon; Bing Ji, Amazon; Stevo Bailey, Amazon; Deepak Shivaru, ; Nilabja Chattopadhyay, ; Sankalp Dayal

 Session Chair: Peter George

  • [1086] Don’t Go Changing: How to Code Immutable UVM Objects 

    • William Moore, Paradigm Works

  • [1077] User Programmable Targeted UVM Debug Verbosity Escalation 

    • Sam Mellor, Arm

  • [1119] Sequencer Containers - A Unified and Simple Technique to Execute Both Sequences and Virtual Sequences

    • Clifford Cummings, Paradigm Works, Inc.; Mark Glasser, Independent Consultant

 Session Chair: Harry Foster

  • [1083] Accelerating Pre-Silicon Verification Coverage with Transaction Sequence Modeling 

    • Jayanth Raman, Micron, Inc.; Jackson Wydra, Micron, Inc.; Ximin Shan, Micron, Inc.; Rahul Krishnamurthy, Micron, Inc.; Michael Yan, Micron, Inc.; Phyllis Hsia, Micron, Inc.; Vikram Narayan, Micron, Inc.; Samir Mittal, Micron, Inc.     

  • [1100] AI - accelerating coverage closure using intelligent stimulus generation 

    • Jainender Kumar, Samsung Semiconductor India Research Bengaluru, India; Ronak Bhatt, Samsung Semiconductor India Research Bengaluru, India; Garima Srivastava, Samsung Semiconductor India Research Bengaluru, India; Ashutosh Sinha, Cadence Design Systems Pvt Ltd Noida, India; Prashant Teotia, Cadence Design Systems Pvt Ltd Noida, India        

  • [1135] A Low-cost yet effective coverage model for fast functional coverage closure 

    • Koushik Ramakrishnan, Nvidia corporation; Roshan Paul, Nvidia corporation; Suresh M K, Nvidia corporation; Ajay Rupanagudi, Nvidia corporation; Tathagato Bose, Nvidia corporation; Guru Venkatesh, [email protected]; Vaidyanathan Sambasivan, Nvidia corporation; Subodh Prabhu, Nvidia corporation

Session Chair: Bhaskar Vedula

  • [1103] Expedite multi-die coherency verification through adaptive VIP subsystem 

    • Jainender Kumar, Samsung Semiconductor India Research Bengaluru, India; Sunil Shrirangrao Kashide, Samsung Semiconductor India Research Bengaluru, India; Garima Srivastava, Samsung Semiconductor India Research Bengaluru, India; Dimitry Pavlovsky, Cadence Design Systems Pvt Ltd, USA; Anunay Bajaj, Cadence Design Systems Pvt Ltd Noida, India        

  • [1120] Leverage Real USB Devices for USB Host DUT verification 

    • Suchir Gupta, Synopsys Inc; Amit Sharma, Synopsys Inc 

  • [1015] Design scheme for Emulator-friendly  Memory Verification IP  to Accelerate Simulation Performance

    • Sunghyeon Kang, SK Hynix; Munsik Bae, SK Hynix; Jinsung Song, SK Hynix; Seokho Hong, Siemens EDA; Minsung Kang, SK Hynix; Sangkyoo Jeong, SK Hynix

 Session Chair: Cliff Cummings

  • [1107] Guardians of the Chip: Mastering Next-Gen Security for SoCs and IPs 

    • Sridevi Jagata, Cadence Design Systems; Deep Mehta, Cadence Design Systems; Vishnu Prasad K V, Cadence Design Systems          

  • [1059] VerifLLMBench: An Open-Source Benchmark for Testbenches Generated with Large Language Models 

    • Nishanth Somashekara Murthy, University of Minnesota, Twin Cities; Eldon Nelson, Synopsys; Sachin Sapatnekar, University of Minnesota, Twin Cities; John Sartori, University of Minnesota, Twin Cities         

  • [1088] Test bench Framework for Fully Automated Register Tests of Numerous IPs in SoC 

    • Wonyeong So, Samsung electronics; Minje Kim, Samsung electronics; Jihye Lim, Samsung electronics; Sunil Roe, Samsung electronics; Youngsik Kim, Samsung electronics; Sunil Choi, Samsung electronics 

 Session Chair: Jamie Ridgeway

  • [1128] Catching the Elusive Voltage Spike with Analog/Mixed-Signal SVA/PSL Assertions 

    • Charles Dancak, Betasoft Inc.

  • [1060] Addressing Advanced Mixed-Signal Verification Scenarios by Developing a UVM Framework for Analog Models 

    • Simul Barua, Ulkasemi Inc.; Henry Chang, Designer’s Guide Consulting, Inc.; Shahriar Kabir, Ulkasemi Inc.         

  • [1057] Reuse of System-level Circuit Models in Mixed-Signal Verification 

    • Bahaa Osman, Cirrus Logic; Minghua Li, Cirrus Logic; Siddharth Maru, Cirrus Logic; Bhanu Singh, Mathworks; Eric Cigan, Mathworks; Suhas Belgal, Mathworks