This workshop presents a comprehensive exploration of machine learning (ML) techniques applied to functional verification, addressing the pressing need to automate and accelerate key stages of chip design verification. As verification consumes approximately 55% of ASIC/IC project costs and is a major bottleneck in chip design schedules, ML offers promising solutions to enhance productivity and reduce time-to-market. Our workshop aims to bridge the gap between cutting-edge research and practical industry applications, providing attendees with actionable insights and strategies to implement ML in their verification processes. 

The workshop begins with a state-of-the-art survey of ML applications in verification, including recent advancements in using large language models (LLMs) for test bench generation and assertion insertion. We will discuss current limitations and challenges in applying ML to complex, large-scale designs, setting the stage for our exploration of novel solutions.