Introduction 
Glitches are a common phenomenon in chip design, often deemed inconsequential due to their occurrence on synchronous paths, where Static Timing Analysis (STA) effectively mitigates them. However, specific scenarios within the chip design flow remain critically vulnerable to glitches, potentially causing catastrophic failures at the silicon level. These critical scenarios include clock domain crossing paths, interfaces between analog and digital domains, reset and clock paths, Design for Testability (DFT) paths, and paths spanning across power domains. Traditional methodologies struggle to detect and address glitches across such diverse scenarios comprehensively. This workshop introduces a holistic static methodology to achieve a thorough glitch signoff.

Summary of the content of the workshop 
The session begins by delineating the glitch phenomenon, followed by a discussion on the existing chip design flow's limitations, which may overlook glitch issues, leading to silicon failures. The workshop will showcase actual glitch-induced design failures encountered by Real Intent's team, including:

• Glitches in asynchronous clock domain paths

• Glitches in reset paths

• Glitches in synchronous multi-cycle paths

• Glitches affecting DFT paths

• Glitches in power domain crossing paths and isolation signals

• Glitches at the digital-to-analog interfaces

We will provide a comprehensive analysis of these glitch types through detailed block diagrams, elucidating the identification, verification, and resolution processes for each glitch type. Drawing from these examples, we will develop a methodological framework that ensures a thorough glitch signoff. 

Furthermore, the session will detail a signoff workflow that integrates static and formal analysis techniques to achieve a robust glitch pathway signoff. 

Concluding with a compilation of Static Signoff best practices derived from industry insights and experiences, this workshop aims to empower participants to elevate verification practices within their organizations. 

Intended Audience 
This workshop is tailored for RTL Designers, Verification Engineers, SoC Designers, Chip Architects, and professionals involved in Clocks and Resets design and architecture, seeking to enhance their verification methodologies against glitches. 

By attending, participants will gain invaluable insights into glitch analysis and signoff strategies, enriching the verification standards and practices in their respective fields.