Arti Dwivedi, Group Director, Product Engineering, Cadence Design Systems 
Yash Bhagwat, Senior Emulation Verification Engineer at NVidia
Michael Young, Senior Product Management Group Director, Cadence Design Systems 

Performance per watt is a key success criteria for complex billion gate SOCs. Optimizing for performance per watt requires power estimation for real application workloads early in the design flow.  

Palladium Dynamic Power Analysis (DPA) offers novel technologies to estimate power of real-world scenarios spanning billions of cycles for billion gates designs in hours. Palladium’s fast dynamic power analysis enables identification of power-hotspots in the design and provides insights into power efficiency of software-hardware interaction. 

This workshop will present the power estimation methodologies for different types of emulation workloads to drive design power efficiency with fastest turnaround for long vectors. The presentation will include case studies on how Palladium users have drastically improved the turnaround of power estimation for long emulation vectors compared to traditional power methodologies. Presentation will also share how Palladium users have improved methodologies for IR drop analysis using DPA, enabling power integrity sign-off for real worst case power scenarios.