DVCon U.S. 2027 Announces Jyotika Athavale as Invited Keynote Speaker and Opens Call for Panel Proposals
Keynote will explore scaling silicon-level functional safety and hardware dependability for increasingly complex autonomous vehicle systems
GAINESVILLE, Fla. — September 29, 2026 — The 2027 Design and Verification Conference and Exhibition (DVCon U.S.), sponsored by Accellera Systems Initiative, today announced Jyotika Athavale, a leader in silicon functional safety at Waymo, as its invited keynote speaker. The conference also announced that panel proposals are being accepted through November 1, 2026. DVCon U.S. 2027 will take place March 1–4 at the Hyatt Regency Santa Clara in Santa Clara, California.
Athavale is currently scheduled to present her keynote, “Safe by Design: Transforming AV Silicon Integration,” on Wednesday, March 3, 2027 at 1:00 p.m. (program details are subject to change).
Keynote Abstract: The compute demands of next-generation high-performance computing (HPC) and artificial intelligence (AI) accelerators are driving unprecedented integration, pushing ASIC architectures to complexity levels previously unseen in mission-critical, ultra-large-scale applications. Ensuring functional safety and hardware dependability at this scale presents a massive challenge for silicon architects and safety engineers because traditional, localized methodologies for safety analysis, fault injection, and FMEDA can no longer keep pace with heterogeneous, multi-billion transistor designs. The industry is currently hitting a "complexity wall," exacerbated by fragmented data formats across disparate EDA toolchains and IP blocks.
The keynote will address how the high-performance silicon ecosystem can scale silicon-level functional safety and hardware dependability through standardized interoperability and advanced on-chip safety mechanisms. She will explore key features essential for building verifiably robust silicon, including In-System Test (IST) for periodic hardware health checks, Software Diagnostic Libraries (SDL) to augment hardware self-testing capabilities, and comprehensive Silicon Lifecycle Management (SLM) to monitor and predict device behavior from manufacturing to end-of-life. These mechanisms, when coupled with a unified data exchange format, are critical for robust fault detection, mitigation, and proving safety and reliability intent.
“We are thrilled to welcome Jyotika as the invited keynote speaker for DVCon U.S. 2027,” stated Xiaolin Chen, DVCon U.S. 2027 General Chair. “Her extensive experience in functional safety, hardware reliability, and advanced silicon technologies gives her a unique perspective on one of the industry’s most pressing challenges. As increasingly complex silicon becomes central to autonomous and other mission-critical systems, her insights into scalable safety methodologies, interoperability, and lifecycle management will be especially valuable to the DVCon U.S. community.”
Background on Jyotika Athavale
Jyotika Athavale is a globally recognized leader in automotive functional safety and hardware reliability, with a career spanning influential organizations in the semiconductor and autonomous vehicle industries. Throughout her tenure at Waymo, NVIDIA, Intel, and Synopsys, Jyotika has pioneered research and industrial practices that bridge the gap between silicon-level integrity and system-level safety.
A central figure in the development of global engineering standards, Jyotika has held key leadership roles within the IEEE as President Emeritus of the IEEE Computer Society and Chair of IEEE P2851 Standards, shaping the methodologies that govern modern automotive and avionics technologies. Her expertise lies at the intersection of high-performance heterogeneous computing and the rigorous demands of automotive safety standards. Today, Jyotika continues to drive the evolution of "Safety-by-Design," ensuring that the next generation of autonomous hardware is both performant and inherently trustworthy.
Call for Panel Submissions
DVCon U.S. 2027 is inviting proposals for a highly focused panel discussion that is lively, thought-provoking, and relevant to the hardware design and verification community. Proposals should emphasize audience engagement and the exchange of ideas—not formal paper presentations—and bring together practical experience with forward-looking perspectives on emerging technologies, industry trends, and future challenges. The one-hour panel will take place on Wednesday, March 3, 2027. For more information and submission guidelines, visit the panel submission page on the DVCon U.S. website.
The technical program is still being finalized. For the latest updates, visit the DVCon U.S. 2027 website.
Registration will open in October. Registration for the keynotes, panel, and exhibits is free.
To view proceedings from past conferences, visit the archives site.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP), and electronic design automation (EDA) companies. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., visit the DVCon U.S. website. Follow DVCon U.S. on Facebook, LinkedIn or @dvcon_us on X or to comment, please use #dvcon_us.
For more information, please contact:
Laura LeBlanc Smith
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Barbara Benjamin
HighPointe Communications
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