1019: RTL Transformation Methods to Achieve Order of Magnitude TAT Improvement in VLSI Design

A typical VLSI implementation starts from a logical or architectural view of the design in RTL, where multiple building blocks are connected without considering physical constraints. This view then goes through a series of modifications required to meet structural design (SD) and manufacturability needs. While some of these modifications enjoy automation through industry standard EDA tools (e.g., DFT insertion), majority of them are currently implemented manually by designers and are considered regular design activity. To make matters worse, some of these steps often need to be repeated based on the feedback from the downstream consumers of the design. In this paper we demonstrate that, with the recent advancements of the EDA industry, many of these activities can now be automated in the form of RTL Transformation. Such transformations include, but are not limited to, Physical Hierarchy restructuring, Feedthrough/Tie-off/Repeater insertion, Clock/Reset re-distribution, Fuse isolation etc. Our methods combine user spec and home-grown code with industry standard EDA tools to achieve RTL transformations on the fly as part of the RTL generation flow. This is a paradigm shift in RTL development, resulting in order of magnitude improvement in design turn-around time (TAT). We describe several applications/transformations from a production use case where multiple weeks of design work have been either fully eliminated or reduced to a fraction of the original TAT, depending on the type of the transformation. We also present various best-known methods (BKMs) and gotchas that need to be considered while performing RTL transformation to achieve the best results, given the current state of the EDA tools.