Endri Kaja, Infineon Technologies AG; Nicolas Gerlin, Infineon Technologies AG; Ungsang Yun, Infineon Technologies AG; Jad Al Halabi, Infineon Technologies AG; Sebastian Prebeck, Infineon Technologies AG; Dominik Stoffel, Rheinland-Pfälzische Technische Universität; Wolfgang Kunz, Rheinland-Pfälzische Technische Universität; Wolfgang Ecker, Infineon Technologies AG
In this paper, we introduce an automated and versatile framework designed to generate diverse SFI campaigns and at the same time closing the gap between the specifications and the fault injection process with minimal efforts. The framework provides a vendor-independent solution, thus all Verilog/SystemVerilog-based simulators/emulators can be utilized. Initially, an RTL generation flow is utilized to generate the designs in a mixed RTL/gate-level granularity and at the same time to equip them with fault injection capabilities. In this flow only selected parts of the design that are subjected to fault injection are kept at the gate-level granularity while the remaining parts of the design are represented at the RTL granularity. This approach enables fast RTL fault simulation while maintaining the accuracy of the gate-level fault simulation to provide automatic SFI on various RISC-V variants.
