Suhas D S, Intel; Ponsankar Arumugam, Intel; Deepmala Sachan, Intel; Ritesh Jain, Intel
Graphics SOCs are high-performance complex design with multiple clocks and reset interacting between multiple modules having CDC/RDC scenarios. Typical Graphics SOC contains hundreds of IP's and multiple Subsystems having 100’s of clocks, where abstract of these are used at SoC for hierarchical analysis which in turn results in 1000's of architectural assumptions. A single wrong assumption can mask the actual violation and lead to metastability. Reviewing large number of constraint's manually is always error prone. In this paper we are addressing such metastability issues by validating these constraints against the actual design intent during simulations to ensure no misses leading to potential silicon escapes.
