1065: Shift Left on Timing Constraints Verification: Beyond Typical Front-End Execution

Timing constraint verification plays a crucial role in the development of GFX SOCs as it ensures that the timing constraints used for synthesis and timing closure are proper and accurate so that the design meets the desired performance requirements. The conventional method used to verify the timing constraints is a gate-level simulation (GLS). Simulations such as these require long run times, offers less coverage, and occurs too late in the design development cycle. A powerful alternative to GLS is the formal verification of timing constraints which is faster and more efficient. The major drawback to this approach is that it may not be entirely possible to formally verify all the timing exceptions in the design and in such scenarios all the formal failures must be verified using SV assertions in functional simulation. However, the sheer number of assertions generated corresponding to the formal failures can make it difficult to verify them completely in simulation. This paper presents the methodology to improve the formal verification and consequently reduce the assertions generated to converge on real timing issues as fast as possible.