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Poster Session

1088: On Analysis of RDC issues for identifying Reset tree design bugs and further strategies for Noise Reduction

Tuesday, March 5, 2024

Farhad Ahmed, Siemens EDA; Manish Bhati, Siemens EDA; Lyle Benson, Siemens EDA

Abstract – Reset tree checks should be viewed thoroughly before reset domain crossing analysis. Static verification tools have many checks for reset tree analysis. The paper discusses on the usage of non-resettable registers (NRRs) in reset paths. NRRs can bring in metastability in the reset paths and hence a thorough verification is a must. The paper also discusses noise reduction strategies in RDC analysis. Stable paths and functional false paths are the focus of the discussion in noise reduction, and we discuss various scenarios and how static verification tool should report these paths.