1131: Towards Efficient Design Verification – Constrained Random Verification using PyUVM

Python, as a multi-paradigm language known for its ease of integration with other languages, has gained significant attention among verification engineers recently. Python-based verification environment capitalizes on open-source frameworks such as PyUVM providing (Python-based UVM 1.2 implementation) and PyVSC (facilitates constrained randomization and functional coverage). These libraries play a pivotal role in expediting test development and hold promise in reducing setup costs. The goal of this paper is to evaluate the effectiveness of PyUVM verification testbenches across various design IPs aiming a comprehensive comparison of their features and performance metrics with the established SystemVerilog-UVM methodology.