Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. We are composed of a broad range of members that fully support the work of our technical committee to develop technology standards that are balanced, open, and benefit the worldwide electronics industry. Leading companies and semiconductor manufacturers around the world are using our electronic design automation (EDA) and intellectual property (IP) standards in a wide range of projects in numerous application areas to develop consumer, mobile, wireless, automotive, and other “smart” electronic devices. Through an ongoing partnership with the IEEE, standards and technical implementations developed by Accellera Systems Initiative are contributed to the IEEE for formal standardization and ongoing governance.

1141: A UVM SystemVerilog Testbench for Directed and Random Testing of an AMS Low-Dropout Voltage Regulator

Tuesday, March 5, 2024 11:00 am — 12:30 pm

A standard UVM testbench is developed to apply benchtop-style directed tests to an on-chip low-dropout CMOS voltage regulator. Eight directed tests verify the regulator's DC and AC response to line and load fluctuations, its programmed operating modes, etc. To enhance the effectiveness of the low-level directed tests in reaching unexpected corner cases, we employ high-level UVM randomization techniques to generate a randsequence of transient tests. The sub-cycle timing aspects of stimulus and response for transient testing are handled using the global uvm_event_pool. Our goal is to present the UVM testbench mechanisms and coding techniques that proved most effective for an area of analog/ mixed-signal testing which lies outside the usual scope of chip-level UVM testbench development.