Santosh Kumar, Qualcomm Technologies Inc; Yogish Raja, Qualcomm Technologies Inc; Geetika Agrawal, Qualcomm Technologies Inc; Karthikeyan Sugumaran, Qualcomm Technologies Inc; Arjun Vazhayil, Qualcomm Technologies Inc; Tommy Brunansky, Qualcomm Technologies Inc.
Ever increasing design complexity across different market segments (Auto, Mobile, Servers, Compute etc.) and different architecture types (single die vs chiplets) has put verification effort and strategies used across IP, Subsystem and SOC under the spotlight. With challenging TTM (time to market) for products, it is imperative to have a scalable verification approach that allows single constrained random stimulus specification to be re used across different verification environments and strategies.
In this paper, we will see our experience of using Portable Test and Stimulus Standard (PSS) language to enable seamless reusability of constraint random scenarios across platforms, design integration levels and verification environments.
