[1004] A Survey of Predictor Implementation using High-Level Language Co-simulation
- Sean Little, Verus Research
[1008] Automating Datapath Verification and Bug Correction via Equality Saturation
- Emiliano Morini, Intel Corporation; Samuel Coward, Intel Corporation; Theo Drane, Intel Corporation; Rafael Barbalho, Intel Corporation; George Constantinides, Imperial College London
[1027] Technical Documents Version Management System Based on Large Language Models
- Siarhei Zalivaka, SK Hynix
[1028] Continuous Integration in SoC Design: Challenges and Solutions
- Wei Liu, sudoinfotech; Jianjun Li, sudoinfotech; Liangfeng Yang, sudoinfotech; Liang Li, sudoinfotech
[1031] Enhancing SDC Verification in SoCs: Heatmap Visualization and Machine Learning Approaches for Optimal Coverage Closure
- Seungkyu Baek, Samsung Electronics; Jaein Hong, Samsung Electronics; Moonki Jun, Samsung Electronics; Sungcheol Park, Samsung Electronics
[1033] A Hybrid Verification Approach for Cache Coherent Systems: Functionality and Performance
- Jiang-Tang XIao, Mediatek; Yung-Cheng Chen, Cadence; Harish Peta, Cadence; Osmond Yao, Mediatek
[1035] An Effective Digital Logic Verification Methodology of High-Speed Interface IP Using a Configurable AFE Behavioral and C hannel Model
- Kiyoon Shim, Samsung electronics; Beomseok Kang, Samsung electronics; Seungsik Eom, Samsung electronics
[1036] Breaking the Formal Verification Bottleneck: Faster and More Comprehensive Testing of Parameterized Modules
- Menachem Rappaport, Veriest; Ariel Ansbacher, Veriest; Elchanan Rappaport, Veriest
[1039] Time-travel Debugging for High-level Synthesis Code
- Jonathan Bonsor-Matthews, LightBlue Logic Limited; Greg Law, Undo Limited
[1046] Static Structural Analysis and Formal Verification of SoC with Software Safety Mechanisms for Functional Safety
- Hyunsun Ahn, Samsung Electronics Co., Ltd.; Euisang Yoon, SIEMENS EDA; Namyul Cho, SIEMENS EDA; Arun Gogineni, SIEMENS EDA; Ann Keffer, SIEMENS EDA; Sungjin Park, SIEMENS EDA; Sungyun Yoo, SIEMENS EDA; Bumju Kim, Samsung Electronics Co., Ltd.; Junhyuk Park, Samsung Electronics Co., Ltd.; Youngsik Kim, Samsung Electronics Co., Ltd.; Seonil Brian Choi, Samsung Electronics Co., Ltd.
[1069] Robust Verification of Clock Tree Network using “Clock Monitor” Integrated by ACRMG
- Tejas Dipakkumar Dalal, Samsung Semiconductor India Research; Giridhar S, Samsung Semiconductor India Research; Jeevan Nataraju, Samsung Semiconductor India Research; Garima Srivastava, Samsung Semiconductor India Research
[1078] Real-time synchronization of C model with UVM Testbench
- Kirtan Mehta, onsemi
[1084] Reset Sweep Verification for Elimination of Reset Domain Crossing Blind Spots in Design
- Nitika Gupta, NXP Semiconductors; Neha Srivastava, NXP Semiconductors; Vivek Yadav, NXP Semiconductors
[1089] Register Access by Intent: Towards Generative RAL based Algorithms
- Ahmed Allam, ICpedia
[1098] Achieving Full Liveness Proofs via a Systematic Assume-Guarantee Approach and Iterative Helper Generation
- Stella Simic, Qualcomm; Karthik Baddam, Qualcomm
[1104] Formal and Simulation Methods Unite to Rescue the Damsel in Distress—Unclassified Faults
- Siri Rajanedi, Analog Devices India pvt ltd; Prashantkumar Ravindra, Analog Devices India pvt ltd
[1112] Traversing the Abyss : Formal exploration of intricate state space
- Sakthivel Ramaiah, Cadence Design System; Tanishq Sharma, Cadence Design System; Craig Deaton, Cadence Design System
[1134] Sleipnir: Bringing constraints and randomization to software defined data types
- Nikhil Soraba, Microsoft; Leon Cao, Microsoft