• GPUs have evolved from large 3D graphics accelerators into massively parallel programmable processors optimized for accelerating GenAI training and inference. With Moore’s law ended, generational gains now rely on aggressive architectural innovation within strict power, thermal, and cost constraints, even as design size, software content, and heterogeneity continue to grow. At the same time, first-silicon success is approaching statistical impossibility as traditional verification flows struggle with software-driven behavior and an exploding state space. Drawing on two decades of experience building GPUs along this trajectory, this talk will examine how design and verification tools and methodologies have adapted to manage both exploding complexity and a sharply increasing development cadence, and how emerging AI-driven agentic workflows across RTL design and verification are becoming essential to sustain the push toward ever more complex GPUs and SoCs on ever faster schedules.

  • As semiconductor systems evolve toward software-defined, AI-driven, and increasingly modular architectures, verification challenges are no longer driven solely by design size. Instead, correctness increasingly emerges from interacting behaviors—across hardware and software, power and performance states, workloads, and execution platforms—transforming verification from a linear, phase-based activity into a continuous, feedback-driven process.

    This keynote brings together three complementary perspectives to examine this shift. An architectural view explores how the meaning of complexity has changed, as interacting system behaviors and iterative verification loops increasingly shape productivity limits beyond what isolated optimizations can address. A hardware-assisted verification perspective examines why faithful execution across simulation and acceleration platforms is essential to expose these behaviors. A practitioner’s perspective then grounds these ideas in real-world experience, describing how a large engineering organization is integrating generative and agentic AI into its verification flows, the challenges of doing so consistently at scale, and the open questions that remain—how to measure productivity, ensure quality, and build trust.

    Together, these perspectives highlight why future verification approaches must be connected across silos, data-driven across iterations, and scalable in human judgment to reason holistically about system behavior throughout the product lifecycle.

    • Abhi Kolpekwar - Siemens SVP-GM DVT.jpg
      Abhi Kolpekwar

      Sr. Vice President, Digital Verification Technology, Siemens EDA

    • Jean-Marie-Brunet-Photo-600x600.jpg
      Jean-Marie Brunet

      Sr. Vice President, Hardware Assisted Verification, Siemens EDA

    • Alon profile.jpg
      Alon Shtepel

      Senior Director, ASIC Verification and Emulation, Micron Technology