2026 Keynote Presentations

GPUs have evolved from large 3D graphics accelerators into massively parallel programmable processors optimized for accelerating GenAI training and inference. With Moore’s law ended, generational gains now rely on aggressive architectural innovation within strict power, thermal, and cost constraints, even as design size, software content, and heterogeneity continue to grow. At the same time, first-silicon success is approaching statistical impossibility as traditional verification flows struggle with software-driven behavior and an exploding state space. Drawing on two decades of experience building GPUs along this trajectory, this talk will examine how design and verification tools and methodologies have adapted to manage both exploding complexity and a sharply increasing development cadence, and how emerging AI-driven agentic workflows across RTL design and verification are becoming essential to sustain the push toward ever more complex GPUs and SoCs on ever faster schedules.

Verification confidence increasingly depends on how real workloads interact with complex, chiplet-based hardware and on delivering power performance KPIs at the system level in a target application environment. As AI and hyperscale systems become software-defined, system behavior emerges from firmware, operating systems, power states, performance, and workload concurrency rather than isolated RTL blocks. This shift exposes limitations in traditional, block-centric verification flows, where late-stage failures increasingly arise at hardware–software and cross-die boundaries.

This keynote examines what has changed and why conventional verification struggles to scale or shift-left in this environment, and how connected verification—spanning simulation to emulation to prototyping —enables earlier and more continuous validation of system behavior. It explores how these engines must be coordinated rather than optimized in isolation, and how agentic orchestration can connect the journey from specifications through RTL to system-level execution. The result is a verification model that reasons holistically about system behavior, supporting software-defined, chiplet-based systems throughout their lifecycle rather than treating verification as a single design phase.

Putting this new flow in a real-world context, the program will welcome a senior D&V engineering executive to share their vision of how they see their teams leveraging these capabilities to address their projects’ challenges.