Is AI the Key to Ending the Verification Bottleneck?"
Verification is the largest driver of time and cost in modern semiconductor projects, often consuming up to two-thirds of total development effort. Debugging and coverage closure dominate this workload, creating long, iterative loops between design and verification teams. Traditionally, “shift left” methodologies have sought to empower designers to verify more of their own work earlier in the cycle—but steep learning curves for verification tools have limited adoption.
AI—especially large language model (LLM)-powered assistants—offers a new way forward. These tools can generate complete, high-quality verification assets from natural-language design intent, automate simulation and formal runs, and produce actionable debug reports in minutes. Advocates see this as the breakthrough that will make “design with verification” a reality. Skeptics question whether AI can handle the complexity, corner cases, and predictability demands of industrial-scale verification.
This panel will bring together leaders in AI, EDA, and semiconductor design to debate whether AI is truly the key to ending the verification bottleneck—or just the next over-hyped technology.