Stuart Sutherland Best Paper Award
1st Place
Properly Introducing Python to your UVM Testbench
Matthew Ballance, AMD
2nd Place
Visualizing SystemVerilog and UVM
Jamie Ridgeway, Paradigm Works
3rd Place
FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures
Yunsheng Bai, NVIDIA; Ghaith Bany Hamad, NVIDIA; Chia-Tung (Mark) Ho, NVIDIA; Syed Suhaib, NVIDIA; Haoxing (Mark) Ren, NVIDIA
Stuart Sutherland Best Poster Award
1st Place
plusargs++: Make Plusargs Great … Like They Never Were Before
Bryan Morris, Ciena Corp, and Michael Silveira, Ciena Corp
2nd Place
There and Back Again: Simulation-to-Synthesis Scenario Reuse with PSS
Tom Fitzpatrick, Big Fish EDA
3rd Place
Taming Configuration Complexity: A UVM-Based Approach To IP Verification
Bhaskar Vedula, Intel Corporation; Ganesh Sharma, Intel Corporation; Stephen Haake, Intel Corporation; Chandrakanth Betageri, Intel Corporation
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