• [23] Application of Metamorphic Testing to Mixed Signal Systems with Behavioral Models 

  • Daniel Cross, Cadence Design Systems

• [28] Taming Configuration Complexity: A UVM-Based Approach To IP Verification 

  • Bhaskar Vedula, Intel Corporation; Ganesh Sharma, Intel Corporation; Stephen Haake, Intel Corporation; Chandrakanth Betageri, Intel Corporation

• [38] Elementary Subpart Extraction, Enabling True Shift-left in Safety Analysis for Closing Architectural Vulnerabilities and Reducing Fault Injection Iterations 

  • Luc Baudoin, AMD; Vedant Garg, Synopsys

• [51] Accelerating SDC Coverage Closure Using ML and LLM-Based Approaches 

  • Seungkyu Baek, Samsung Foundry; Jiyong Kwon, Samsung Foundry; Jaein Hong, Samsung Foundry; Sungcheol Park, Samsung Foundry

• [53] Multi-Agent Orchestration for Autonomous Regression Management 

  • Sangwoo Noh, Samsung; Jin Choi, Samsung; Seunghee Yim, Samsung

• [62] There and Back Again: Simulation-to-Synthesis Scenario Reuse with PSS 

  • Tom Fitzpatrick, Big Fish EDA

• [64] Towards Self-Adaptive SoC Design Verification: KG-Enhanced Generative AI, RL and Backpropagation Debugging 

  • Insu Jang, Samsung Electronics; Seonghee Yim, Samsung Electronics; Hanna Jang, Samsung Electronics; Seonil Brian Choi, Samsung Electronics

• [68] An Efficient Random Instruction Sequence Generation for Verification of Domain Specific Architecture Processor 

  • Wonjae Lee, Samsung Electronics Co., Ltd.; Youngsub Ko, Samsung Electronics Co., Ltd.; Yelim Han, Samsung Electronics Co., Ltd.; Doowon Lee, Samsung Electronics Co., Ltd.; Dahyun Yoo, Samsung Electronics Co., Ltd.; Heewon Ahn, Samsung Electronics Co., Ltd.; Joongbaik Kim, Samsung Electronics Co., Ltd.

• [71] Integrating Formal Methods with Lightweight Testing for Automotive Firmware Verification 

  • Bryan Olmos, Infineon Technologies Dresden AG & Co. KG; Shuhang Zhang, Infineon Technologies AG; Wolfgang Kunz, Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau; Djones Lettnin, Infineon Technologies AG

• [81] RTL Performance Isn’t Just a Number - It’s a Story 

  • Olivera Stojanovic, Vtool; Hagai Arbel, Vtool

• [85] plusargs++: Make Plusargs Great … Like They Never Were Before 

  • Bryan Morris, Ciena Corp; Michael Silveira, Ciena Corp

• [92] An Approach to Create Scalable Power Management Verification Environment 

  • Pranav Mopkar, Intel Corporation

• [98] AI Agent-based Specification Matching System for SoC RTL Verification 

  • Yonghyun Kwon, Samsung Electronics; Hanna Jang, Samsung Electronics; Seonghee Yim, Samsung Electronics

• [122] RISC-V reuse made easy by interface generation and integration automation 

  • Ares Tahiraga, Infineon Technologies; Said Llukaj, Infineon Technologies; Wei Zhao, Infineon Technologies; Endri Kaja, Infineon Technologies; Sebastian Prebeck, Infineon Technologies; Wolfgang Ecker, Infineon Technologies

• [134] Saarthi for AGI: Towards Domain-Specific General Intelligence for Formal Verification 

  • Aman Kumar, Infineon Technologies India Private Limited; Deepak Narayan Gadde, Infineon Technologies Dresden AG & Co. KG; Minh Luu, Infineon Technologies Vietnam Company Ltd.; Keerthan Kopparam Radhakrishna, Infineon Technologies Dresden AG & Co. KG; Vaisakh Naduvodi Viswambharan, Infineon Technologies Dresden AG & Co. KG; Sivaram Pothireddypalli, Infineon Technologies India Private Limited

• [147] GLS Shift Over Through Timing Constraint Verification: A Comprehensive Framework 

  • Amey Telang, Samsung Semicondutor India Research; Sunil Kashide, Samsung Semicondutor India Research; Garima Srivastava, Samsung Semicondutor India Research; Shekhar Sharma, Samsung Semicondutor India Research; Karishma Singh, Cadence

• [165] IP-XACT Based PSS Modeling for Shift-Left SoC Verification 

  • Moonki Jang, Samsung Electronics Co.,Ltd; Yonghyun Yang, Samsung Electronics Co.,Ltd; Kangho Lee, Samsung Electronics Co.,Ltd; Yejin Lee, Samsung Electronics Co.,Ltd; Youngchan Lee, Samsung Electronics Co.,Ltd; Sunil Roe, Samsung Electronics Co.,Ltd; Youngsik Kim, Samsung Electronics Co.,Ltd; Seonil Choi

Session Chair: Jamie Ridgeway

• [102] AI Driven Advanced Debugging in SoC Design Verification 

  • Shreya Jayatheerth Joshi, Samsung Semiconductors India R&D; Alok Kumar, Samsung Semiconductors India R&D; Poonam Shettar, Samsung Semiconductors India R&D; Sanjoy Saha, Samsung Semiconductors India R&D; Shrinidhi S Rao, Samsung Semiconductors India R&D; Garima Srivastava, Samsung Semiconductors India R&D

• [123] Streamlining RAL-based Cross-Coverage and Sequence Coverage through Automation 

  • Vijayakrishnan Rousseau, Intel Corporation; Satyajit Sinari, Intel Corporation; Ram Immaneni, Intel Corporation; Mangayarkarasi Arumugam, Intel Corporation; Raghavendra CK, Intel Corporation; Prasad Shah, Intel Corporation

• [111] Beyond Heuristics: AI/ML Driven Verification for Design Sign-off 

  • Gulshan Sharma, Samsung Semiconductor India Research; Sougata Bhattacharjee, Samsung Semiconductor India Research; Avinash Bollu, Samsung Semiconductor India Research; Abhishek Raj, Samsung Semiconductor India Research; Akshaya Jain, Samsung Semiconductor India Research

Session Chair: Tom Fitzpatrick

• [176] Early FMEDA at RTL for Functional Safety, Correlating RTL Metrics to GLS for Accurate Architectural Analysis 

  • MyungKyoon Yim, Hyundai; Vedant Garg, Synopsys; Buyong Um, Hyundai; Kyle Kim, Synopsys; Liz Song, Synopsys

• [174] Closing the Safety Verification Loop, FMEDA-Driven Fault Simulation and Advanced Debug for Efficient Fault Classification 

  • Sagar Hema Vidya, AMD; Vedant Garg, Synopsys; Sudhakar Chappidi, AMD; Sharon monica Kurmana, AMD

• [94] Optimizing Functional Fault Grading Flow for Memory Designs 

  • Euisang Yoon, Siemens EDA; Arun Gogineni, SiemensEDA; Eunjong Oh, Samsung Electronics; Seongwook Lee, Samsung Electronics; Sungyun Yoo, Siemens EDA; Geonbeom Kwon, Siemens EDA; Yoseop Lee, Samsung Electronics; Hyojin Choi, Samsung Electronics; Saurabh Srivastava, Siemens EDA

Session Chair: Karan Arora

• [84] A GPT-2 Tabular Transformer Model for Automated DRAM Verification 

  • Lorenzo Ferretti, Micron Technology; Chinmaya Behera, Micron Technology; Shailesh Sharma, Micron Technology; Nihar Athreyas, Micron Technology; Vikram Narayan, Micron Technology; Samir Mittal, Micron Technology

• [89] From Specification to Closure: A Semi-Automated Coverage-Driven Verification Methodology for Cache Coherent Home Nodes 

  • Kavin Rajendran, OPENEDGES Square, Corp.; Anish mon Soosai, OPENEDGES Square, Corp.; Kranthi Konganti, OPENEDGES Square, Corp.; Shivaprasad Naranapura Chandrashekara Swamy, OPENEDGES Square, Corp.

• [63] A Platform-Based Approach to Reduce Verification Turn-Around Time in Memory Designs 

  • Junho An, Samsung Electronics; Seonyong Lee, Samsung Electronics; Gyehyun Na, Samsung Electronics; Minseon Kim, Samsung Electronics; Dongeun Lee, Samsung Electronics; Jaehyun Park, Synopsys; Kiuk Kim, Synopsys

Session Chair: Karan Arora

• [84] A GPT-2 Tabular Transformer Model for Automated DRAM Verification 

  • Lorenzo Ferretti, Micron Technology; Chinmaya Behera, Micron Technology; Shailesh Sharma, Micron Technology; Nihar Athreyas, Micron Technology; Vikram Narayan, Micron Technology; Samir Mittal, Micron Technology

• [89] From Specification to Closure: A Semi-Automated Coverage-Driven Verification Methodology for Cache Coherent Home Nodes 

  • Kavin Rajendran, OPENEDGES Square, Corp.; Anish mon Soosai, OPENEDGES Square, Corp.; Kranthi Konganti, OPENEDGES Square, Corp.; Shivaprasad Naranapura Chandrashekara Swamy, OPENEDGES Square, Corp.

• [63] A Platform-Based Approach to Reduce Verification Turn-Around Time in Memory Designs 

  • Junho An, Samsung Electronics; Seonyong Lee, Samsung Electronics; Gyehyun Na, Samsung Electronics; Minseon Kim, Samsung Electronics; Dongeun Lee, Samsung Electronics; Jaehyun Park, Synopsys; Kiuk Kim, Synopsys

Session Chair: Peter George

• [182] Effective Methodologies to Accelerate Security Verification 

  • Lee Anthony Grajo, Analog Devices; Ponnambalam Lakshmanan, Analog Devices; Anders Nordstrom, Cycuity

• [143] LFSR: Beyond the Sequential - Unlocking the Potential of Immediate Nth Cycle Output 

  • Kshiteej Kosambia, Cadence; Prakash Darji, Cadence

• [47] Security Verification in Practice: Lessons from Pre-Silicon Analysis of SoC Subsystems 

  • Yashwanth Kumar, Marvell Technology, Inc.; Rachana Maitra, Marvell Technology, Inc.

• [121] Threat Modeling for SoC Security Design: IEEE P3164 SA-EDI Standardization 

  • Wenzhen Li, IEEE P3164

Session Chair: Harry Foster

• [57] Enhancing Automotive ECU Design with Digital Twin Simulation: Comparative Study of Virtual Platform, FPGA Prototyping, and Edge Device Configurations 

  • Sara Abd AlWahab, Electronics and Communications Engineering Department, Cairo University; Mohamed AbdElsalam, Siemens Digital Industries Software; Ahmed H. Khalil, Electronics and Communications Engineering Department, Cairo University; Hassan Mostafa, Electronics and Communications Engineering Department, Cairo University

• [69] An AI Agent Framework with Elasticsearch for Scalable Post-Silicon Debug Automation 

  • Minuk Lee, Samsung Electronics; Hanna Jang, Samsung Electronics; Seonghee Yim, Samsung Electronics; Youngsik Kim, Samsung Electronics

• [79] AI-Driven Adaptive Emulation for Accelerated Pre-Silicon Debug: High-Fidelity Silicon Replay

  • Sampathkumar M Ballary, Samsung Semiconductor India Research; Priyadarshini Pai, Samsung Semiconductor India Research; Aruna S Lohiya, Samsung Semiconductor India Research; Ramesh G Patgar, Samsung Semiconductor India Research; Karthik Srinivasan, Samsung Semiconductor India Research; Vemuri Krishna Sumanth, Samsung Semiconductor India Research; Vandana S, Samsung Semiconductor India Research; Venkata Subba Rao Manne, Samsung Semiconductor India Research; Subrata Sarkar, Samsung Semiconductor India Research; Samruddhi C R

• [166] Accelerating Bare Metal Driver Development with Linux Drivers and System Verilog DPI-C.

  • Suchir Gupta, Synopsys; Amit Sharma, Synopsys; Suneetha Suryadevara, Synopsys; Vishnuvardhan Reddy, Synopsys

Session Chair: Vibarajan Viswanathan

• [127] A New Methodology for Formal Equivalence Checking of Sorting Algorithms 

  • Emiliano Morini, NVIDIA

• [25] ConnChecker: Automated Root-Cause Analysis for Formal Connectivity Check via Graph 

  • Ngoc Tiep Do, Infineon Technologies; Linh Anh Nguyen, Cornell University; Danh Minh Luu, Infineon Technologies

• [65] Early Deep Bug Discovery via Re-run Acceleration and Parallel Multi-Depth BMC Exploration 

  • Jungwoo Seo, Samsung Electronics Co., Ltd.; Dongyoung Kim, Samsung Electronics Co., Ltd.; Sungjin Park, Siemens EDA; Mark Eslinger, Siemens EDA; Juyeon Son, Samsung Electronics Co., Ltd.; Gyehyun Na, Samsung Electronics Co., Ltd.; Dongeun Lee, Samsung Electronics Co., Ltd.

• [58] Scaling Formal Verification of Network On Chip Using Path Decomposition 

  • Bilal Ahmed, 10x Engineers; Umar Yaqoob, 10x Engineers; Bilal Zafar, 10x Engineers; Misbahud DIn, Lahore University of Management and Sciences

Session Chair: Santosh Kumar

• [118] EVM - Enhanced Verbosity Methodology 

  • Gergő Vékony, ARM; József Mózer, ARM

• [124] Automated Root-Cause Analysis of GPU Pipeline Corruptions in Graphics and Compute Workloads 

  • Pravesh Dangwal, Intel; Himanshu Somaiya, Intel; Leena Singh, Intel

• [181] A Novel ML-driven simulation Log Debugger 

  • Narasimha Rao Chinni, Samsung semiconductor india research; Sunil Shriragrao Kashide, Samsung semiconductor india research; Garima Srivastava, Samsung semiconductor india research

• [139] Passive Token Accounting: Managing LLM Cost in Continuous Verification 

  • Ajith Jose, Dhenara Inc

• [164] Visualizing SystemVerilog and UVM 

  • Jamie Ridgeway, Paradigm Works

• [34] Integrating RTL design and UVM Testbench with Hyperledger Blockchain and Machine Learning for better efficiency and optimization 

  • Sougata Bhattacharjee, Samsung Semiconductor India Research

• [91] Exploring UVM TLM2 based Sequence, Sequencer and Driver in UVM 

  • Neha Goyal, Nvidia Corporation; Justin Refice, Nvidia Corp

• [26] Harnessing Volatility: Innovative Strategies for Register Synchronization in UVM RAL 

  • Bhaskar Vedula, Intel Corporation; Stephen Haake P, Intel Corporation; Chandrakanth Betageri, Intel Corporation

Session Chair: Kamel Belhous

• [54] A 3-Tiered Agentic AI Framework for Verification Regression 

  • Jin Choi, Samsung Electronics; Sangwoo Noh, Samsung Electronics; Seunghee Yim, Samsung Electronics

• [52] A Novel Fast Regression: An AI/ML Driven Automated Sanity Regression Flow 

  • Joonho Chung, Samsung Electronics; Daeseo Cha, Samsung Electronics; Woojoo Space Kim, Samsung Electronics; Youngsik Kim, Samsung Electronics; Seonil Brian Choi, Samsung Electronics; Nili Segal, Cadence Design Systems

• [117] Etabot: Multi‑Agent Verification Management with Chat‑Accessible Midpoint Metrics and Finish-Date Forecasts 

  • Zili Fang, Silicon Labs

Session Chair: Benjamin Ting

• [177] Real-Time Performance Insights: AI-Accelerated Trace-Driven Analysis for Multi-GPU Pre-Silicon Verification Environments 

  • Vinoth Selvan, NVIDIA Corporation; Prashanth Rajan, NVIDIA Corporation

• [19] Database Driven RTL Simulation: Fighting Billion-Gate Verification Bottlenecks 

  • Victor Besyakov, BTA Design Services

• [67] Unified AI-Driven Verification: Combining Spec-RAG, Memory Networks, and Generative AI 

  • Seonghee Yim, Samsung Electronics; Insu Jang, Samsung Electronics; Hanna Jang, Samsung Electronics; Seonil Brian Choi, Samsung Electronics

Session Chair: Bhaskar Vedula

• [149] Properly Introducing Python to your UVM Testbench 

  • Matthew Ballance, AMD

• [46] Breaking the Wait: Customizable, Real-Time Post-Processing for Data Integrity Verification in SerDes Systems 

  • Chandana K Nallangi, Intel; Suresh S Gandhi, Intel

• [22] A Modern Debug Paradigm: Python Visualization For DDR Memory Controller’s Performance Analysis 

  • Pallavi Kumar, AMD; Michael Chan, AMD