2026 Tutorials & Workshops

Johannes Stahl, Synopsys 
Rob Parris, Synopsys

Today’s conventional wisdom is that you need the fastest and highest capacity verification engines to tackle the hardware and software complexity of complex multi-die systems. Those teams that are just thinking about these aspects are in for a rough awakening. Without a full range of protocol solutions matching the IP to their verification engines, they can spend months before they can run the 1st system validation test. Participants of this tutorial will learn what it takes to validate a protocol with state-of-the-art solutions.

In the first 90 minutes of the tutorial, we will highlight what state-of-the-art protocol solutions need to offer and how they are practically used.

In the second 90 minutes of the tutorial, we will pick selected protocol solutions and go deep into explaining what's inside. We will show practical examples that the audience will also be able to see in a live demo on the show floor.

Jean-Christophe Brignone, STMicroelectronics
Farhad Ahmed
Anupam Bakshi
Chetan Choppali Sudarshan
Bill Gascoyne
Don Mills
Iredamola Olopade

CDC-RDC analysis has evolved as an inevitable stage in RTL quality signoff in the last two decades. Over this period, the designs have grown exponentially to SOC’s having 2 trillion+ transistors and chiplet’s having 7+ SOC’s.

Different vendor tool abstracts are seen because of multiple IP vendors, even in house teams might deliver abstracts generated with different vendors tools.

The Accellera CDC Working-Group aims to define a standard CDC-RDC IP-XACT / TCL model to be portable and reusable regardless of the involved verification tool.

As moving from monolithic designs to IP/SOC with IPs sourced from a small/select providers to sourcing IPs globally (to create differentiated products), the quality must be maintained as driving faster time-to-market. In areas where the standards (SystemVerilog, OVM/UVM, LP/UPF) are present, the integration is able to meet the above (quality, speed). However, in areas where standards (in this case, CDC-RDC) are not available, most options trade-off either quality, or time-to-market, or both :-( Creating a standard for inter-operable collateral addresses this gap.

This tutorial aims to remind the definitions of CDC-RDC Basic Concepts and constraints, as well as the description of the reference verification flow, and addressing the goals, scope, structure & deliverables of the Accellera CDC Working Group in order to elaborate a specification of the standard abstract model.

A status related to the last LRM version open to public review by 2025-Q4, will be presented.

Darron May, Siemens EDA 
Mark Carey, Siemens EDA 
Dan Yu, Siemens EDA 
Karim Ameziane, Siemens EDA 
Chandu Challapalli, Siemens EDA 
Ronen Shoham, Siemens EDA
Joe Hupcey III, Siemens EDA 

The escalating complexity of modern System-on-Chip (SoC) designs challenges traditional RTL signoff, creating bottlenecks in design creation and RTL signoff. This tutorial introduces a transformative paradigm: applying Agentic AI to intelligently automate and optimize the entire design-to-signoff process, moving beyond static flows to a dynamic, intelligent ecosystem that’s capable of autonomous reasoning and adaptation; supporting engineers from initial concept and design exploration through final, comprehensive verification.

Central to this strategy is the novel Model Context Protocol (MCP), a standardized semantic communication layer that transforms IC design and verification tools into active, context-aware participants by exposing real-time design state, creation parameters, and tool capabilities. This enables a rich, shared understanding, allowing tools to publish critical information and respond intelligently, effectively merging design exploration and verification.

Leveraging MCP, platform-agnostic Agentic AI frameworks orchestrate complex tasks across design and verification domains. These agents are empowered to reason, plan, adapt, and execute strategies dynamically. They assist in design space exploration, architectural optimization, rapid iteration, identifying critical verification paths, generating targeted stimulus, intelligent debug, and root-cause analysis with minimal human intervention. This drives significant acceleration for design and verification closure, reducing cycle times and improving signoff quality.

The approach is engineer-centric, providing intuitive guidance to configure and deploy these advanced AI capabilities, fostering a collaborative human-AI partnership. This tutorial will detail the architectural principles behind this Agentic AI approach, demonstrating how MCP facilitates interoperability and enables autonomous, trusted RTL signoff. Attendees will gain insights into fostering design quality and liberating engineers from repetitive tasks.

William Wang, ChipAgents 
Mehir Arora, ChipAgents 
Kexun Zhang, ChipAgents

The semiconductor industry faces relentless pressure to shorten design cycles, improve quality, and manage escalating complexity. Traditional EDA tools have made remarkable progress, yet verification still consumes the majority of project schedules and resources. Recent breakthroughs in large language models and agentic AI present a transformative opportunity: autonomous, task-oriented agents that can collaborate with engineers in design and verification workflows.

This workshop explores the promise and limitations of AI agents applied to RTL design, debug, and verification. We will demonstrate how agentic systems can generate UVM testbenches, accelerate coverage closure, and automate tedious debugging tasks, all while integrating seamlessly with existing toolchains through standard EDA workflows. At the same time, we will examine the critical challenges that remain: ensuring correctness and determinism, handling corner cases, and scaling performance across large design teams.

Participants will gain a grounded understanding of where AI agents add real value today, what open problems the community must address, and how engineers can adopt these tools responsibly. Through case studies and interactive discussion, we will highlight early successes, industry feedback, and research directions that could reshape how verification is performed in the next decade.

Whether you are a verification engineer, design engineer, or decision-maker, this session will help you separate hype from reality and envision a future where AI agents become trusted fellow engineers in the chip design process.

Xiaolin Chen, Synopsys 

Formal verification offers unmatched rigor in ensuring design correctness, but its adoption is often hindered by steep learning curves, manual effort, and delayed integration into the design flow. This workshop explores how artificial intelligence (AI) is transforming formal verification into a more accessible, scalable, and efficient methodology from the earliest stages of development.

We will demonstrate how AI can intelligently guide assertion generation, property selection, and proof strategies—dramatically reducing setup time and increasing coverage. By learning from design patterns, verification history, and specification intent, AI enables earlier deployment of formal methods, improves usability for non-experts, and accelerates convergence for seasoned practitioners.

Through real-world examples and tool demonstrations, attendees will gain practical insights into AI-augmented formal verification workflows that deliver faster results, higher confidence, and reduced human effort. Whether you’re a verification engineer, formal expert, or RTL designer, this session will show how to harness AI to make formal easier to adopt and more impactful than ever before.

Rohan Ganpati, Cadence Design Systems 
Michael Young, Cadence Design Systems 
Lance Tamura, Cadence Design Systems
Jun-Wei, Lin, Skymizer

The rapid growth in semiconductor design activity is projected to increase in the coming years, however, RTL design and verification remains a significant challenge in semiconductor development. While emulation is widely adopted to accelerate verification, today, most emulation technologies cater to the needs of large-scale ‘billion-gate’ class designs.

Many design teams across various organizations create IP or small-scale yet mission-critical ASIC/SoC designs and strive to leverage emulation. Unfortunately, existing emulation solutions are often inaccessible to these teams due to constraints such as limited capital budgets, low priority in resource allocation, or lack of data center infrastructure.

To lower the barrier of adoption, Cadence introduced the Dynamic Duo System Studio, comprising the Palladium Z3 System Studio and the Protium X3 System Studio. The Palladium Z3 System Studio is a standalone emulation appliance tailored to emulate designs up to 128 million gates, with software and tool flows compatible with the enterprise-scale Palladium Z3 system.

In this session, we intend to present the benefits and features of the Palladium Z3 System Studio-- a leading-edge emulation appliance that significantly lowers the adoption barrier for design and verification teams, enabling them to accelerate hardware/software co-verification workloads via emulation.

We also intend to share case studies from companies specializing in AI chip development and other mission-critical applications. These case studies will demonstrate how design teams achieved multi-thousand-fold performance improvements over simulation, shortened verification cycles, and accelerated software bring-up by several months through the adoption of System Studio into their workflows. 

Torin Schlunk, ChipAgents 
Mehir Arora, ChipAgents 
William Wang, ChipAgents

In the past year, AI agents have moved from research prototypes into production EDA environments. At the forefront of this transition is ChipAgents, an agentic AI system purpose-built for RTL design and verification. Since its introduction, ChipAgents has been deployed across leading semiconductor companies, engaging with design engineers, verification teams, and toolchain owners on real projects. This workshop shares what we have learned from those deployments: the successes, surprises, and lessons that can guide the broader adoption of agentic AI in EDA.

We will present case studies where ChipAgents accelerated UVM testbench development, improved coverage closure, and reduced debug turnaround time, while also discussing scenarios where agents encountered limitations and required human guidance. Particular emphasis will be placed on integration patterns: how ChipAgents accelerate a variety of workflows, how teams structured evaluations, and which workflows benefited most from agentic AI.

Just as importantly, we will cover the challenges discovered in practice: from handling complex corner cases, to measuring ROI, to work with production environments. Audience members will gain an honest perspective on both the potential and the practical hurdles of introducing agentic AI into high-stakes semiconductor design and verification flows.

By distilling insights from one year of real-world usage, this session aims to equip engineers, managers, and researchers with actionable knowledge on how to evaluate, adopt, and scale AI agents responsibly in their own verification environments. 

Russell Klein, Siemens EDA 
Mark Azadpour, AWS

High-Level Synthesis (HLS) is an established design methodology that raises the abstraction level for design and verification. Verification at the abstract level runs much faster than RTL level simulations. But abstract simulations cannot completely verify the implementation, as it omits certain RTL details. For a complete verification, some verification must be performed at the RTL level.

This talk will describe a design flow that enables FPGA prototype verification of an HLS synthesized module using an Amazon AWS F2 instance as the FPGA prototyping system. AWS F2 instances provide 8 AMD Virtex UltraScale+ HBM VU47P FPGAs on a PCIe card, with DPI and C++ interfaces. The HLS synthesized RTL module is run through the Xilinx tools to program the FPGAs. The HLS C++ testbench, and its associated results checking and coverage, can be reused to with the module loaded into the FPGAs. This enables the proven testbench environment from the HLS flow to be used with a full RTL implementation of the module. Bus interfaces, memories, and interrupt logic can all be modeled and verified at the RTL level, these structures are often abstracted away in High-Level Verification flows.  FPGA prototyping can be an ideal complement to High-Level Verification in an HLS design flow.  Using cloud-based FPGA instances on AWS eliminates the need for hardware acquisition and management, and can scale up and down as needed based on verification demands. 

Vikas Sachdeva, Bangalore

This workshop, titled "Liberating Functional Verification from Boolean Shackles", emphasizes the growing importance of static signoff in early-stage functional verification. It highlights how static methods, unlike traditional Boolean-based simulation and formal techniques, offer faster, scalable, and easier verification—crucial for handling today’s complex SoC designs. Covering real-world case studies and best practices, the session demonstrates how early RTL static signoff improves design quality, reduces re-spins, shortens time-to-market, and enhances security. It’s aimed at RTL designers, verification engineers, and chip architects seeking efficient, shift-left verification strategies.

Amir Attarha, Siemens

From battery operated handhelds to datacenter servers, electronic devices are defined by their power characteristics. Depending on the application area, total power consumption varies based on the semiconductor (SoC) content used, and the intended purpose for the device. One truth applies to every SoC, power analysis requires a holistic methodology from architectural exploration to tape-out to accurately addresses power concerns. 

One of the key factors used to calculate power consumption is the dynamic power that has become increasingly important in technologies such as FinFET. Here the gate area has increased; hence, the load capacitance is larger and the impact of the switching power more pronounced.

In this workshop, join us in exploring the power dynamics shaping the future of the data centric era, with a focus on the growing influence of artificial intelligence. We’ll examine emerging methodologies for power profiling and analysis and their positive impact on meeting power requirements and how AI is transforming the way we approach SoC power. 

Tobias Ludwig, LUBIS EDA 
Osama Ayoub, LUBIS EDA

Writing SystemVerilog Assertions (SVA) is a must-do task when applying Formal Verification, more particular FPV. Not only is this a highly specialized and manual task, fulfilling the completeness-criteria and making sure that the full functionality and state-space of the design is covered can be tricky.

We will introduce the Property Generator, a tool that generates a complete set of SystemVerilog Assertions (SVA) from SystemC-based models. This enables formal verification to begin as early as the virtual prototyping phase. It results in correct-by-construction assertions, quick turn- around in case requirement changes, and, lastly, removes the need for human review of the assertions.

We aim to introduce the tool to a wider audience and help people starting their formal verification journey.

By leveraging state-of-the-art compilers and integrating AI-powered refinement, the Property Generator eliminates the need for manual property creation, accelerating verification workflows and reducing review overhead. This workshop demonstrates how behavioral intent, captured in SystemC, can be directly translated into actionable formal properties, leading to bug-free RTL designs with less manual eQort and greater confidence. 

Robert Ruiz, Synopsys 
Chun Chan, Synopsys

This session highlights breakthrough AI-powered advancements in debug workflows for RTL design and verification, featuring state-of-the-art capabilities of the Synopsys Verdi platform. Attendees will learn how Verdi's intelligent technology leverages sophisticated artificial intelligence (AI) to enhance collaborative problem-solving, streamline data analysis, and facilitate multi-level debug across simulation, emulation, formal, and static verification environments. Integration with Synopsys verification tools and popular development environments enables users to interact with Verdi for a range of investigative and diagnostic tasks.

Through practical examples and a live demonstration, the session will showcase how next-generation AI can accelerate root cause analysis, suggest effective solutions, and enable comprehensive, data-driven debug strategies. Key features—including advanced interactivity, context-aware analysis, and innovative workflow integration—will be explored. Participants will see how Verdi platform's cutting-edge AI capabilities are transforming the debug process for modern silicon development. 

Moshik Rubin, Cadence Design Systems 
Yael Abarbanel, Cadence Design Systems

AI-driven agentic workflows are redefining functional verification by automating tasks traditionally handled through extensive manual effort. Agentic AI systems can ingest specifications and autonomously generate verification artifacts, reason across verification intent, and coordinate with other agents to accelerate closure on coverage and quality goals.

This workshop will present the Cadence Verification Silicon Agent, which transforms a specification into executable verification collateral, including verification plans, UVM environments, and SystemVerilog assertions. Attendees will see how AI agents enable traceability from intent to implementation while reducing setup and maintenance overhead.

We will also detail recent innovations in Cadence Verisium AI, spanning regression management and debug automation. Topics include intelligent testcase selection, coverage-aware regression orchestration, automated gap analysis for verification planning, AI-driven failure triage, bug prediction based on historical patterns, and waveform analysis with context-aware root cause extraction.

By combining agentic generation with AI-enhanced orchestration and debug, these flows shift verification engineers’ focus from repetitive setup and analysis toward architectural validation and signoff, ultimately improving productivity and silicon quality.

Tim Schneider, Arteris
Insaf Meliane, Arteris
Alvin Santos, Arteris

Modern System on Chip (SoC) designs involve many components: Hardware Description Languages (VHDL, System Verilog), Unified Power Format (UPF), Software Languages (C#/C++), Interconnect standards (IPXACT, AMBA) and purpose built layers such as the Universal Verification Methodology (UVM) and System Verilog Assertions (SVA).

This tutorial explores SoC Integration technologies to ""blend"" these components together, proposing a more efficient methodology to increase productivity and ensure first-time SoC project success. The example design combines RISC-V processor elements, Arteris IP and AMBA Peripherals, “blending” together the various standards such as CSRSpec, System Verilog, UPF and IP-XACT into a complete SoC system. Index Terms – SoC Integration; IP-XACT; System Verilog; UVM; Hardware Software Interface, RISC-V.

Georgios Passas, Arteris 
Aiyush Aggarwal, Agnisys 
Freddy Nunez, Agnisys 
Thomas Burg, STMicroelectronics

As System-on-Chip (SoC) designs grow in scale and complexity, integration teams face significant challenges in managing registers, memory maps, IP packaging, and verification collateral. Traditional methods based on spreadsheets or proprietary
formats often result in inconsistencies, delays, and costly rework. 

IEEE 1685-2022 (IP-XACT), developed by Accellera, provides a vendor-neutral framework to describe, package, and integrate IP. The 2022 revision introduces an updated schema, richer register and memory map support, and enhanced mechanisms for capturing hierarchy and connectivity. These improvements enable consistent design data exchange across design, verification, and software teams, while supporting greater automation and reuse.

This training workshop provides participants with a practical understanding of IP- XACT 2022 and how to apply it in real SoC projects.