Sponsored Tutorial

Monday, March 2, 2026

• System Validation - It's the Protocol Stupid

  9:00 am — 10:30 am • Tutorial

  Johannes Stahl, Synopsys Rob Parris, Synopsys

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• TvastaaVP: An Agentic AI Approach to SystemC

  1:50 pm — 3:00 pm • Tutorial

  Shravan Kumar Belagal Math, Vayavya Labs Pvt Ltd; Rajat Shetty, Vayavya Labs Pvt Ltd; Karthick Gururaj, Vayavya Labs Pvt Ltd; Sandeep Pendharkar, Vayavya Labs Pvt Ltd

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Accellera Tutorial

Thursday, March 5, 2026

• Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model

  9:00 am — 10:30 am • Tutorial

  Jean-Christophe Brignone, STMicroelectronics; Farhad Ahmed, Siemens; Anupam Bakshi, Agnisys; Chetan Choppali Sudarshan, Marvell; Bill Gascoyne, Blue Pearl Solutions; Don Mills, Arm; Iredamola Olopade, Google; Devendra Gupta, Agnisys

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Sponsored Workshop

Thursday, March 5, 2026

• Agentic AI for RTL Signoff

  9:00 am — 10:30 am • Workshop

  Darron May, Siemens EDA; Ronen Shoham, Siemens EDA; Joe Hupcey III, Siemens EDA

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• Broadening the Adoption of Hardware-Assisted Verification with Next Generation Emulation Appliance

  9:00 am — 10:30 am • Workshop

  Rohan Ganpati, Cadence Design Systems; Michael Young, Cadence Design Systems; Lance Tamura, Cadence Design Systems; William Wei, Skymizer

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• High-Level Synthesis Meets FPGA Prototyping in the Cloud

  1:30 pm — 3:00 pm • Workshop

  Sivasankar Palaniappan, Siemens EDA; Mark Azadpour, AWS

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• Power Dynamics: Shaping the Future of the Data Centric Era and the Role of AI

  11:00 am — 12:30 pm • Workshop

  Amir Attarha, Siemens

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• Transforming Verification Debug: AI Innovations with Verdi

  1:30 pm — 3:00 pm • Workshop

  Chun Chan, Synopsys

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• Verification in the Agentic AI era - A whole new ball game!

  11:00 am — 12:30 pm • Workshop

  Moshik Rubin, Cadence Design Systems; Yael Abarbanel, Cadence Design Systems

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Monday, March 2, 2026

• AI Agents for Design and Verification: Opportunities and Challenges

  1:30 pm — 3:00 pm • Workshop

  William Wang, ChipAgents; Mehir Arora, ChipAgents; Kexun Zhang, ChipAgents

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• AI Meets Formal: Practical Applications from Industry Leaders

  1:30 pm — 3:00 pm

  Xiaolin Chen, Synopsys; Bindumadhava S S, Google; Ghaith Bany Hamad, Nvidia; Pradip Prajapati, Synopsys

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• ChipAgents in Practice: Lessons from One Year of Agentic AI EDA Deployment

  3:30 pm — 5:00 pm • Workshop

  Torin Schlunk, ChipAgents; Mehir Arora, ChipAgents; William Wang, ChipAgents; Luke Frey, ChipAgents

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• Liberating Functional Verification from Boolean Shackles

  9:00 am — 10:30 am • Workshop

  Vikas Sachdeva, Bangalore

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• Property Generator: Simple Generation of Formal Assertion IP

  11:00 am — 12:30 pm • Workshop

  Dr. Tobias Ludwig, LUBIS EDA

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• Automate the Pain Away: HW/SW Interface Design Methodology

  3:30 pm — 5:00 pm • Workshop

  Tim Schneider, Arteris; Insaf Meliane, Arteris; Alvin Santos, Arteris

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Accellera Workshops

Thursday, March 5, 2026

• IP-XACT Demystified: An In-Depth Training on the IEEE 1685-2022 IP-XACT Standard

  1:30 pm — 3:00 pm • Workshop

  Georgios Passas, Arteris; Aiyush Aggarwal, Agnisys; Freddy Nunez, Agnisys; Thomas Burg, STMicroelectronics; Richard Weber, Arteris

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Monday, March 2, 2026

• Portable Stimulus Modeling Patterns (Practical Tips for Adopting PSS)

  9:00 am — 10:30 am • Workshop

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