Session 1: Low Power UPF

Session Chair: Progyna Khondkar

• [1082] Refinable Macros and Terminal Boundaries in UPF 4.0: Empowering Soft IPs of the Future 
  • Amit Srivastava, Synopsys Inc; John Decker, Cadence Design Systems; Lakshmanan Balasubramanian, IEEE & ACM
• [1127] Applications for UPF HDL Supply Tunneling in Mixed Signal Design 
  • Daniel Cross, Cadence Design Systems
• [1136] Future Proofing Power Intent Specification through Unified Power Format 4.0 for Evolving Advanced State Retention Strategies 
  • Lakshmanan Balasubramanian, IEEE, ACM & Texas Instruments (India) Pvt. Ltd.; Amit Srivastava, Synopsys Inc.; Raguvaran Easwaran, Intel India Pvt. Ltd.; John Decker, Cadence Design Systems; Rick Koster, SIEMENS EDA; Progyna Khondkar, Cadence Design Systems; Paul Bailey, Nordic Seminconductors; Barry Pangrle, Abacus Semiconductor Corporation; Shreedhar Ramachandra, Synopsys Inc.; Phil Giangarra, Cadence Design Systems; John Biggs, IEEE; David Cheng, Cadence Design Systems
• [1034] What’s New in IEEE 1801 and Why you Need to Know Now? 
  • Progyna Khonkdar, Cadence Design Systems