1049: Functional Verification Of Analog Devices Modeled Using Sv-Rnm
Mariam Maurice, Siemens EDA
Technical Session 12 [Analog Modeling in SystemVerilog]
1091: Variation-Aware Modeling Method For Mram Behavior Model Using System-Verilog
SangGi Do, Samsung Electronics; Seongeun Shin, Samsung Electronics; JungKyu Jang, Samsung Electronics; Dohui Kim, Samsung Electronics
1156: Sv_Lut: A Systemverilog Look Up Table Package For Developing Complex Ams Real Number Modeling
FNU Farshad, Ulkasemi Inc; Shafaitul Islam Surush, Ulkasemi Inc.; Simul Barua, Ulkasemi Inc