Technical Session 4 [UVM Testbenches]

  • 1031: Leveraging Model Based Verification For Automotive Soc

    Aswini Kumar Tata, ALLEGRO MICROSYSTEMS LLC; Bhanu Singh, MathWorks; Sanjay Chatterjee, ALLEGRO MICROSYSTEMS LLC; Eric Cigan, MathWorks; Surekha Kollepara, ALLEGRO MICROSYSTEMS LLC; Kamel Belhous, Allegro Microsystems

  • 1047: A Uvm Multi-Agent Verification Ip Architecture To Enable Next-Gen Protocols With Enhanced Reusability, Controllability And Observability

    Prathik R, Samsung Semiconductor India Research, Bengaluru; Ramesh Madatha, Samsung Semiconductor India Research, Bengaluru; Girish Kumar Gupta, Samsung Semiconductor India Research, Bengaluru; Tony Gladvin George, Samsung Electronics, Korea

  • 1103: Leveraging Interface Classes To Improve Uvm Tlm

    Neha Goyal, Nvidia Corp.; Justin Refice, Nvidia Corp.

  • 1116: Without Objection - Touring The Uvm_Objection Implementation - Uses And Improvements

    Rich Edelman, Siemens EDA