Tuesday, March 5, 2024

  • Ashfaq Khan, Intel Corporation; Shuhui Lin, Intel Corporation; Daniel Standring, Intel Corporation; Adam Campos, Intel Corporation; Satish Venkatesan, Intel Corporation; Soowan Suh, Intel Corporation

    A typical VLSI implementation starts from a logical or architectural view of the design in RTL, where multiple building blocks are connected without considering physical constraints. This view then goes through a series of modifications required to meet structural design (SD) and manufacturability needs. While some of these modifications enjoy automation through industry standard EDA tools (e.g., DFT insertion), majority of them are currently implemented manually by designers and are considered regular design activity. To make matters worse, some of these steps often need to be repeated based on the feedback from the downstream consumers of the design. In this paper we demonstrate that, with the recent advancements of the EDA industry, many of these activities can now be automated in the form of RTL Transformation. Such transformations include, but are not limited to, Physical Hierarchy restructuring, Feedthrough/Tie-off/Repeater insertion, Clock/Reset re-distribution, Fuse isolation etc. Our methods combine user spec and home-grown code with industry standard EDA tools to achieve RTL transformations on the fly as part of the RTL generation flow. This is a paradigm shift in RTL development, resulting in order of magnitude improvement in design turn-around time (TAT). We describe several applications/transformations from a production use case where multiple weeks of design work have been either fully eliminated or reduced to a fraction of the original TAT, depending on the type of the transformation. We also present various best-known methods (BKMs) and gotchas that need to be considered while performing RTL transformation to achieve the best results, given the current state of the EDA tools.

  • Kaiwen Chin, Renesas; Esra Sahin, Renesas; Kranthi Pamarthi, Renesas

    LINT tools have been supporting digital designers to structurally detect design issues early in the design cycle. One of the key problems they seek to address is “arithmetic overflow” detection. Due to inevitable false negatives within pure Structural LINTing flow, designers struggle to isolate the real issues. Manual assessment of certain types of violations can be tedious, error-prone, and very time-consuming. LINT combined with Formal Methods of Analysis offers exciting new opportunities. Formal LINT tools provide efficient Formal-enhanced solutions for many LINTing applications to ensure good design quality. One of the areas of concern is arithmetic overflow verification. Formal-aware LINTing helps designers identify real design issues much more efficiently. However, efficient formal-aware verification requires RTL designers to adopt a certain coding style for signed arithmetic operations. . We have been partnering with EDA vendors to improve reliability and robustness of arithmetic overflow verification in Formal LINT tools, aiming to achieve higher productivity and accuracy. While the tools keep improving in their coverage, this paper recommends the most promising RTL coding style if one wants to use Formal LINT tools to detect arithmetic overflow. The paper illustrates strength of Formal LINT technology over Structural LINTing, summarizes best practices and pitfalls in signed arithmetic RTL implementation, articulates the approach taken in tool evaluations, and briefly presents the tool evaluation results.

  • Kyoungmin Park, Samsung Electronics; Brad Budlong, Cadence Design Systems; Hyundon Kim, Samsung Electronics; Danny Yi, Cadence Design Systems; Gibs Lee, Cadence Design Systems; Jaehunn Lee, Samsung Electronics; Chulmin Kim, Samsung Electronics; Jaemin Choi, Samsung Electronics; Kijung Yoo, Samsung Electronics; Youngsik Kim, Samsung Electronics; Yogesh Goel, Cadence Design Systems; Seonil Brian Choi, Samsung Electronics

    This paper introduces an innovative 4-State logic ('0', '1', 'X', 'Z') emulation technology and how we applied it to real mobile-AP SOC for power-aware verification for the first time in the emulation based verification world including requirements for successful adoption. And the results of the experiment compared with traditional simulation based verification. Also we share the experimental data about how much additional resources are needed for 4-State logic emulation compared with 2-State logic emulation.

  • Endri Kaja, Infineon Technologies AG; Nicolas Gerlin, Infineon Technologies AG; Ungsang Yun, Infineon Technologies AG; Jad Al Halabi, Infineon Technologies AG; Sebastian Prebeck, Infineon Technologies AG; Dominik Stoffel, Rheinland-Pfälzische Technische Universität; Wolfgang Kunz, Rheinland-Pfälzische Technische Universität; Wolfgang Ecker, Infineon Technologies AG

    In this paper, we introduce an automated and versatile framework designed to generate diverse SFI campaigns and at the same time closing the gap between the specifications and the fault injection process with minimal efforts. The framework provides a vendor-independent solution, thus all Verilog/SystemVerilog-based simulators/emulators can be utilized. Initially, an RTL generation flow is utilized to generate the designs in a mixed RTL/gate-level granularity and at the same time to equip them with fault injection capabilities. In this flow only selected parts of the design that are subjected to fault injection are kept at the gate-level granularity while the remaining parts of the design are represented at the RTL granularity. This approach enables fast RTL fault simulation while maintaining the accuracy of the gate-level fault simulation to provide automatic SFI on various RISC-V variants.

  • Suhas D S, Intel; Ponsankar Arumugam, Intel; Deepmala Sachan, Intel; Ritesh Jain, Intel

    Graphics SOCs are high-performance complex design with multiple clocks and reset interacting between multiple modules having CDC/RDC scenarios. Typical Graphics SOC contains hundreds of IP's and multiple Subsystems having 100’s of clocks, where abstract of these are used at SoC for hierarchical analysis which in turn results in 1000's of architectural assumptions. A single wrong assumption can mask the actual violation and lead to metastability. Reviewing large number of constraint's manually is always error prone. In this paper we are addressing such metastability issues by validating these constraints against the actual design intent during simulations to ensure no misses leading to potential silicon escapes.

  • Seungyeon Yu, Samsung Electronics, Memory Division; Damin Son, Samsung Electronics, Memory Division

    This paper discusses the verification method for microcode-based IP in SSD controller products. As memory products need higher performance, there are large portions of functions that benefit from microcode-centric design than traditional logic-based designs. The advantages of this shift include better flexibility, simpler handling of complex tasks, the ability to reuse code, cost savings, improved performance, and broader compatibility. Microcode is a set of instructions for processor tasks. It allows changes in hardware functions without major redesigns, making design updates faster and easier. But this comes with a greater cost of possible bugs and it's vital to ensure the design is accurate. So, this paper introduces a new way to verify the designs in simulation tests. We explain about how to set up test scenarios and create checkers for functional coverage, emphasizing the transition to microcode. Because microcode is different from regular RTL code, we need a novel way to measure its coverage. We introduce a method for this and also suggest a way to detect and remove any redundant code, aiding in streamlining the design process.

  • Vineeth B, Intel Technology India Pvt Ltd; Deepmala Sachan, Intel Technology India Pvt Ltd; Ritesh Jain, Intel Technology India Pvt Ltd

    Timing constraint verification plays a crucial role in the development of GFX SOCs as it ensures that the timing constraints used for synthesis and timing closure are proper and accurate so that the design meets the desired performance requirements. The conventional method used to verify the timing constraints is a gate-level simulation (GLS). Simulations such as these require long run times, offers less coverage, and occurs too late in the design development cycle. A powerful alternative to GLS is the formal verification of timing constraints which is faster and more efficient. The major drawback to this approach is that it may not be entirely possible to formally verify all the timing exceptions in the design and in such scenarios all the formal failures must be verified using SV assertions in functional simulation. However, the sheer number of assertions generated corresponding to the formal failures can make it difficult to verify them completely in simulation. This paper presents the methodology to improve the formal verification and consequently reduce the assertions generated to converge on real timing issues as fast as possible.

  • Farhad Ahmed, Siemens EDA; Manish Bhati, Siemens EDA; Lyle Benson, Siemens EDA

    Abstract – Reset tree checks should be viewed thoroughly before reset domain crossing analysis. Static verification tools have many checks for reset tree analysis. The paper discusses on the usage of non-resettable registers (NRRs) in reset paths. NRRs can bring in metastability in the reset paths and hence a thorough verification is a must. The paper also discusses noise reduction strategies in RDC analysis. Stable paths and functional false paths are the focus of the discussion in noise reduction, and we discuss various scenarios and how static verification tool should report these paths.

  • Nicholas Nuti, Intel Corporation; Srinivasan Jambulingam, Intel Corporation

    Contemporary methods of validating SoC IP interoperability tend to be arduous and time-consuming because they lack a standardized functional validation methodology. An SoC is made of many interconnected IPs that can be developed and verified in isolated conditions. Lack of initial collaborative effort between IP teams can lead to increased validation complexity because IPs have varying simulation requirements and preexisting work must be modified to directly integrate other IPs. Direct IP integration in interoperability validation will require extended support from other teams during setup because simulations must be merged. Merging IP simulations can be difficult because projects may have imposing requisites. Further, a lack of a standardized and seamless integration method increases project duration and can cause validation teams to find bugs late in the overall development process due to delays. This paper discusses an unobtrusive and accessible method of multi-IP simulation with the aim of optimizing and simplifying the process of interoperability validation

  • Sharada Vajja, Google LLC; Raghu Alamuri, Google LLC; Saksham Mehra, Google LLC

    Mobile System-on-Chip (SoC) devices have entered an era of unprecedented complexity, driven by the exponential growth in hardware capabilities within smartphones and other portable devices. The increased demand to support complex and high performance features in the current smartphones has prompted the integration of compute engines like GPUs, multicore CPUs and other Machine Learning processing units in the mobile chips. This substantially surged the performance demands placed on the mobile devices making performance verification an increasingly critical endeavor in addition to the functional verification.

    In this paper, we present a systematic approach to efficiently capture the intricacies of the performance verification flow, offering insights into strategies, methodologies , stimulus generation, analysis techniques and results. More importantly, this approach is designed to be scalable across various testbenches and environments including SoC modeling, IP and SoC level RTL simulations, emulation and post silicon validation.

  • Emiliano Morini, Intel; Bill Zorn, Intel; Disha Puri, Intel; Madhurima Eranki, Intel; Shravya Jampana, Intel

    Dot Product Accumulate Systolic units are a primary part in the ML accelerator architectures. They compute floating-point matrix multiply-add operations, which consist of several dot products. Given that exhaustive simulation is impossible in real use cases, Formal Verification is the only possible option to verify these components. C2RTL Formal Equivalence Checking has shown to be a very powerful methodology, and to deploy it successfully an independent, trust C/C++ reference model is required. In this paper, we present a comprehensive End-to-End (E2E) Formal Verification Signoff approach for DPAS units. The proposed flow begins with a new formal friendly C++ model, created using an internal iFP library, developed starting from the FPCore functional programming language, and validated against 3rd party trusted libraries. Then the flow continues with a C2RTL equivalence checking to establish the RTL correctness, where the assumptions used are encoded in the RTL itself as SVA properties and tested using simulation and formal property verification. Several hard corner-case bugs have been identified in intermediate versions of the RTL with this methodology. Innovative techniques have been developed to achieve full convergence, in particular for large double precision units, proving that the final RTL doesn’t have any bug against the reference model.

  • Deepak Narayan Gadde, Infineon Technologies; Suruchi Kumari, Infineon Technologies; Aman Kumar, Infineon Technologies

    Python, as a multi-paradigm language known for its ease of integration with other languages, has gained significant attention among verification engineers recently. Python-based verification environment capitalizes on open-source frameworks such as PyUVM providing (Python-based UVM 1.2 implementation) and PyVSC (facilitates constrained randomization and functional coverage). These libraries play a pivotal role in expediting test development and hold promise in reducing setup costs. The goal of this paper is to evaluate the effectiveness of PyUVM verification testbenches across various design IPs aiming a comprehensive comparison of their features and performance metrics with the established SystemVerilog-UVM methodology.

  • Nimay Shah, Analog Devices Inc.; Pranav Dhayagude, Analog Devices Inc.; Paul Wright, Analog Devices Inc.; Raj Mitra, Cadence Design Systems Inc.

    Emulation is ubiquitous for verifying and validating complex silicon systems of today's age, comprising of a full software stack driving highly intricate hardware. However, as some of these silicon systems move towards the edge, the underlying hardware becomes exceedingly mixed-signal with the integration of sensors, real-world interfaces, high-speed data convertors, buck/boost regulators, etc. Traditional emulation techniques only support synthesizable digital logic. As a result, the scope of what can be verified or validated, and to what extent is somewhat limited. This means that software driven chip configuration that goes all the way down to a primitive hardware elements or complex calibration loops and low power techniques involving the full software stack, cannot be fully verified prior to tapeout. This is an absolute necessity in today’s complex systems at cutting edge manufacturing technologies owing to the cost of unplanned tape-outs and the pressure of delivering first-pass sampleable silicon to customers. The novel techniques presented in this paper focus on taking away this limitation and enabling analog/mixed-signal behavioral modeling methods, thereby enabling "true" system-level, mixed-signal emulation.

  • Charles Dancak, Betasoft Inc.

    A standard UVM testbench is developed to apply benchtop-style directed tests to an on-chip low-dropout CMOS voltage regulator. Eight directed tests verify the regulator's DC and AC response to line and load fluctuations, its programmed operating modes, etc. To enhance the effectiveness of the low-level directed tests in reaching unexpected corner cases, we employ high-level UVM randomization techniques to generate a randsequence of transient tests. The sub-cycle timing aspects of stimulus and response for transient testing are handled using the global uvm_event_pool. Our goal is to present the UVM testbench mechanisms and coding techniques that proved most effective for an area of analog/ mixed-signal testing which lies outside the usual scope of chip-level UVM testbench development.

  • Santosh Kumar, Qualcomm Technologies Inc; Yogish Raja, Qualcomm Technologies Inc; Geetika Agrawal, Qualcomm Technologies Inc; Karthikeyan Sugumaran, Qualcomm Technologies Inc; Arjun Vazhayil, Qualcomm Technologies Inc; Tommy Brunansky, Qualcomm Technologies Inc.

    Ever increasing design complexity across different market segments (Auto, Mobile, Servers, Compute etc.) and different architecture types (single die vs chiplets) has put verification effort and strategies used across IP, Subsystem and SOC under the spotlight. With challenging TTM (time to market) for products, it is imperative to have a scalable verification approach that allows single constrained random stimulus specification to be re used across different verification environments and strategies.

    In this paper, we will see our experience of using Portable Test and Stimulus Standard (PSS) language to enable seamless reusability of constraint random scenarios across platforms, design integration levels and verification environments.