Fernando Orge, Allegro MicroSystems
This paper introduces the PyRDV tool, which helps IC (Integrated Circuit) developers find potential coverage holes or unimplemented requirements without running simulations. PyRDV is not just a Python-based software tool but a complete solution consisting of (1) A theoretical framework to prove design completeness, (2) A detailed workflow for IC developers based on GitLab issues, (3) A Python package to collect all the necessary information from the GitLab issues and (4) A CI/CD (Continuous Integration / Continuous Deployment) service to periodically check for sign-off metrics. Thus, this work presents an alternative solution to the requirements traceability problem and contributes to RDV (Requirement-driven Verification) methodologies, proposing detailed criteria to guarantee the implementation of all the requirements and the verification of all the specifications. The theoretical framework defines a common language for all the IC developers, preventing ambiguities in the information flow. The GitLab platform is the unique source of truth among all developers since it gathers requirements, specifications and verification plans. The GitLab CI/CD service also helps publish all the sign-off reports and metrics on the GitLab platform. As a result, developers will benefit from this prompt information because it will help them to quickly adapt to requirement changes and optimize design and verification resources.