1008: Crafting A Million Instructions/Sec RISCV-DV -- HPC Techniques to Boost UVM Testbench Performance by over 100X

High-end RISC cores encompass intricate processor architectures that comprise of complex instruction pipelines and convoluted maneuvers like instruction re-ordering. Functional verification of such cores require a signification effort involving thousands of millions of millions ($10^{15}$) randomized instructions\cite{ARM-verif}. The RISCV-DV project, coded in SystemVerilog, generates about 10,000 instructions in a second. At this rate it may take several machine years to generate the required randomized sequences of RISC-V instructions.