Seokho Lee, FuriosaAI; Youngsik Kim, FuriosaAI; Suhyung Kim, FuriosaAI; Jeong Ki Lee, FuriosaAI; Wooyoung Choe, FuriosaAI; Minho Kim, FuriosaAI
Over the past few years, there has been a growing trend of using Python for design verification instead of traditional hardware verification languages such as SystemVerilog. However, existing Python verification frameworks focus on driving and monitoring signals or solving random constraints, but lack coverage features which makes it hard to achieve functional coverage closure. This paper proposes a Python environment for enabling functional coverage closure. This environment fully utilizes rich features of SystemVerilog functional coverage as well as leverages existing tools for easier coverage analysis.
