Sougata Bhattacharjee, Samsung Semiconductor India Research (SSIR); Gulshan Kumar Sharma, Samsung Semiconductor India Research (SSIR); Wonil Cho, Samsung Electronics; Akshaya Kumar Jain, Samsung Semiconductor India Research (SSIR); James Kim, Siemens; Andrey Likhopoy, Samsung Electronics; Sangkyu Park, Samsung Electronics; Hyeonuk Noh, Samsung Electronics; Ann Keffer, Siemens; Arun Gogineni, Siemens
Functional verification efforts are concentrated on making sure that the design is meeting the expectation as per the specification and that all the functionality has been verified. It will never look for the design's capability to detect or correct itself from random hardware failures. The ability to recover from hazardous and random failure is very important for functional safety. The motivation for this paper is to introduce functional safety-related flows and observe their effect on design correctness. We also present several comparisons that are derived out of results from using different optimization techniques while performing fault simulation either with full fault list generation or with SRF. The paper also pointed out different techniques so that maximum Diagnostic Coverage (DC) can be achieved in minimum time.
