1031: Leveraging Model Based Verification For Automotive SoC

In this paper, we describe how to build model-based testbenches and conduct early testing when design behavior is available as models developed in MATLAB, Simulink, or C/C++ source code. Our approach high-lights reuse of the Simulink test environment in UVM bench development and extension of the generated UVM bench by adding more complex constrained randomizations, assertion checkers, and coverage groups. Collecting model-based coverage, dead logic detection, rollover and saturation checks helped us in finding corner case bugs in the design. In this way, digital verification engineers can benefit from the exhaustiveness that UVM generally provides while shifting the verification effort earlier through the use of model-based benches. Moreover, merging coverage – i.e., code and functional coverage – from the UVM test runs between algorithm blocks and non-algorithm blocks in RTL proves to be much simpler to deliver during coverage sign off. We also share our experience of building a stimulus model that can generate multiple test scenarios. and how to replicate stimulus between model-based test runs and RTL test runs.