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1049: Functional Verification of Analog Devices modeled using SV-RNM

Wednesday, March 6, 2024 3:00 pm — 4:30 pm

As waiting for the completion of the analog transistor level could extend the time to market for the digital verification engineers to ensure that both the analog and the digital systems will function properly when they are connected, the functional verification of the analog devices that are modeled using the Real Number Modeling (RNM) has become a crucial step of the mixed-signal SoC's validation. Given that there are numerous effective, adaptable, and trustworthy functional verification approaches, including the Constrained Random Verification (CRV), Functional Coverage, Assertions/Checkers, and Universal Verification Methodology (UVM). The paper explains how these approaches could be used to test an analog-modeled Device Under Test (DUT) and guarantee its functional accuracy