1055: Unleashing the Power of Whisper for Block-Level Verification in High Performance RISC-V CPU

This paper describes a framework that uses Whisper (an open source RISCV simulator), RISCV assembly and a System Verilog / UVM framework to verify the memory subsystem of an out of order CPU. Load/Store cache and MMU are arguably the most complex microarchitectural blocks in any high-performance CPU. Our methodology enables RTL designers to describe a scenario which is then translated into block level stimulus/drivers with the help of an architectural simulator. This not only reduces the effort for DV engineers for crafting stimulus but also provides more granular control that comes with a block level testbench. Using this technique, we will demonstrate how we enabled a design from scratch and how we were able to take high level language workloads (e.g. operating systems, benchmarks) and seamlessly run them at the block level. This flow also provided a staged enablement of RISCV architectural extensions in our design. We are in the process of creating an interface that allows stimulus generation via ChatGPT. It will effectively allow complex test plan scenarios to be described in plain text and translated into stimulus that can run on a block level testbench!