1062: Tackling Missing Bins: Refining Functional Coverage In Systemverilog For Deterministic Coverage Closure

In the context of hardware design verification, defining function coverage accurately in SystemVerilog remains a challenge, largely due to human errors leading to "missing coverbins". This paper introduces a methodology aimed at enhancing function coverage by identifying these overlooked bins. By treating coverbins as a SystemVerilog queue and employing an "waive function", this approach provides verification engineers a mechanism to efficiently determine whether sampled cover point already accounted for in the coverage. Experimental validation, involving the CacheManager in an SSD Controller, underscored the method's efficacy, with results revealing a significant 16.4% improvement in functional coverage. Thus, the proposed method not only rectifies human-induced inaccuracies but also improves the overall robustness of hardware verification.