As the number of companies developing RISC-V CPUs grows, it is useful to look at the ecosystem around verifying RISC-V cores. Historically companies have had to develop all the tools and techniques for CPU design verification (DV) themselves; verification methodology is usually seen as part of their secret sauce. With many RISC-V CPU companies appearing, developing rigorous verification methodology will be critical to the wide success of the architecture. However it will be impractical for each company to develop their own private verification methodology and tooling.

RISC-V verification tooling efforts today are fragmented across multiple projects and a mix of commercial and open source tools so it’s hard to understand at a glance what can be leveraged from the ecosystem and what might have to be built. While there is value in having a well verified product, in another sense it is a hygiene factor; all successful CPU companies will need high quality verification to succeed. 

This paper will discuss the current state of the RISC-V testing ecosystem before identifying gaps and opportunities. The focus is on simulation based testing. While formal tools are also often used by CPU verification engineers, there are fewer options available and less RISC-V specific innovation.

As the RISC-V ecosystem matures, we can expect to see more complete solutions pulling together all the component elements needed for CPU DV.