1087: Working within the Parameters that SystemVerilog has constrained us to

Modern SoC designs are composed of a large number of blocks, which are typically a mix of internal and third party vendor provided IP. In order to manage the complexity, not only is the reuse of existing IP essential, but modern platform-based design goes one step further in churning out multiple product derivatives by reusing a single configurable base design. Parameterization is at the heart of this reuse methodology. Parameters are well supported in the most widely used Hardware Description Languages (HDL), namely VHDL, Verilog and SystemVerilog. However, on the HVL side in SystemVerilog, the user must contend with various challenges when working with parameterized interfaces, classes and coverage. This work compares various known solutions to the parameterized interface problem. As these solutions do not support parameterized interfaces in an emulation context, a new emulation compatible solution is proposed. The next problem area highlighted is the UVM factory. Whilst working with non-parameterized classes, the UVM factory abstraction (base class & macros) is easy to use without understanding the core implementation. However, to effectively use the factory design pattern with parameterized classes, we need to dig deeper. The final challenge described is related to parametric coverage. Parameterized classes make parametric coverage handling very easy, but as we will see, there are drawbacks to this under specific scenarios. Various solutions to this problem are presented.