1091: Variation-aware modeling method for MRAM behavior model using System-Verilog

IP verification is an essential process when designing solid IPs. In addition, the importance of IP verification is being highlighted due to increased demand for automotive silicon. Verifying the logical operations always requires a behavior model which is written in Verilog or VHDL. From small gates to large memories, behavior models are essential for logical simulation. For small circuits such as gates and standard cells, it is easy to implement all operations. However, large-sized IPs, such as memory, usually reflect only key operations, because it is impossible to implement all the detailed operations and considering physical characteristics. Furthermore, some specialized devices, such as MTJ device for MRAM, have unique probabilistic characteristics that cannot be supported using conventional modeling methods. In this paper, we introduce our memory bit-cell modeling method, which enables various test operations for MRAM. Our proposed modeling methods are implemented for solid IP validation, and they support not only the MRAM but also various types of memories.