Kirolos Mikhael, Siemens EDA; Abelouhab Ayari, Siemens EDA
The increasing complexity of modern System-on-Chips (SoCs) has led to the emergence of numerous subsystems, resulting in the need for broader teams to collaborate on a single chip. Consequently, it has become more challenging to integrate and perform functional verification on both the subsystem and chip level. In the software industry, Continuous Integration (CI) has gained trust as an automated testing and integration solution that reduces time and effort. Thus, can CI be leveraged by hardware professionals to achieve a traceable, seamless, and quicker integration solution? This article will explore the efficacy of using a unified framework comprising of Questa Formal, Design Solutions, and Simulation to execute functional verification and simulation with CI. With this increasing complexity of the system and maybe some wall hitting for the performance of the tools the eyes are now going to how to increase the productivity using the same tools. In this paper, we will show how to utilize the CI flow in hardware to increase the productivity by making the flow more configurable and seamless. Wilson Research reports that 24% of time is spent on creating tests and running simulations, and 41% on debugging. Using continuous integration (CI) in functional verification ensures automation and tight integration between various functional verification tools, resulting in reduced time and effort. This paper will cover the process of building a strong integration and how to use such a flow in hardware verification to achieve higher productivity and quality.
