Prashantkumar Ravindra, Analog Devices; Barry Briscoe, Analog Devices; Miguel Castillo, Analog Devices; Nimay Shah, Analog Devices
Verification IPs are the building blocks of UVM testbenches needed for Metric Driven Verification of complex designs. UVM Testbench generators supply the necessary infrastructure to instantly create a basic UVM testbench template from scratch. However, the VIP integration into the testbench is done manually, making the testbench development activity much more difficult and time-consuming. Automating VIP integration is the solution, but this is not straightforward due to the lack of an industry-wide standard to exchange VIP metadata. In this paper, the authors present a non-proprietary VIP metadata template that can enable this automation via a testbench generator. This paper will further highlight how, without restricting the creativity of VIP developers, multiple vendor VIP titles have been successfully integrated into the ADI's UVM Testbench generator, with the help of this metadata. This enabled the DV engineers to instantly create a ready-to-simulate sophisticated UVM TB from scratch, reducing the efforts from weeks to minutes.