Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. We are composed of a broad range of members that fully support the work of our technical committee to develop technology standards that are balanced, open, and benefit the worldwide electronics industry. Leading companies and semiconductor manufacturers around the world are using our electronic design automation (EDA) and intellectual property (IP) standards in a wide range of projects in numerous application areas to develop consumer, mobile, wireless, automotive, and other “smart” electronic devices. Through an ongoing partnership with the IEEE, standards and technical implementations developed by Accellera Systems Initiative are contributed to the IEEE for formal standardization and ongoing governance.
Neha Goyal, Nvidia Corp.; Justin Refice, Nvidia Corp.
The current Transaction Level Modeling (TLM) specification in the Universal Verification Methodology (UVM) has many shortcomings. It lacks compile-time checks for port and interface compatibility and missing implementations. Additionally, it leaks APIs between different interfaces, allowing nonsensical and illegal method calls that are only detectable at run time. With the introduction of Interface classes in SystemVerilog 2012, we can rethink UVM TLM such that illegal and nonsensical behavior can be detected at compile-time, reducing the latency for the user to address these errors.