1103: Leveraging Interface Classes to Improve UVM TLM

The current Transaction Level Modeling (TLM) specification in the Universal Verification Methodology (UVM) has many shortcomings. It lacks compile-time checks for port and interface compatibility and missing implementations. Additionally, it leaks APIs between different interfaces, allowing nonsensical and illegal method calls that are only detectable at run time. With the introduction of Interface classes in SystemVerilog 2012, we can rethink UVM TLM such that illegal and nonsensical behavior can be detected at compile-time, reducing the latency for the user to address these errors.