Simul Barua, Ulkasemi Inc.; FNU Farshad, Ulkasemi Inc.; Henry Chang, Designer’s Guide Consulting, Inc.
Due to the rise of AI, Internet of Things (IoT), and cloud computing, demand for high-performance computing System on Chips (SoC) is higher than ever. To ensure the correct functionality of these complex SoCs, there is a plethora of digital verification solutions offered by various vendors and in-house verification teams. But in order to ensure first functional silicon we need to perform full-chip verification with both the analog and digital subsystems. Currently, there is no standard methodology for performing full chip verification and existing functional verification solutions focus heavily on UVM-driven digital verification testbenches. Due to the high simulation run time of SPICE models and analog circuits, it is not feasible to run analog circuits in schematics along with UVM testbenches. So, it is desirable to model the functional behavior of analog circuits using a higher-level language such as SystemVerilog, Verilog-AMS, etc. such that they provide full functional coverage, and analog assertions to verify connectivity along with reasonable accuracy and faster simulation run times. In this paper, as much is in the literature on the trade-offs of AMS vs. DMS modeling, we will discuss digital-driven chip-level verification and the trade-offs when using both approaches along with examples to illustrate our approach.
