Nitish Sharma, Qualcomm Inc; Venkata Nishanth Narisetty, Qualcomm Inc
Formal Verification (FV) has established itself as a critical element of high-quality functional verification, playing an indispensable role in the success of tape-out of modern hardware designs. While safety properties have received significant attention in recent EDA tool advancements, liveness properties remain relatively overlooked, even among formal experts. In this work, we introduce a robust mathematical formulation aimed at delving into exploring deep states in the design and uncover liveness issues like starvation, livelocks, and deadlocks etc. Furthermore, we extend this methodology to break down the FV complexity related to liveness, enabling us to achieve exhaustive proofs for liveness properties. We also present the bugs found by this approach in multiple DV signed off designs.
