Rich Edelman, Siemens EDA
The SystemVerilog UVM implements a class named uvm_objection. An objection is used to guard code that isn't done yet". For example, an objection can prevent a process from finishing until some other process agrees. Uvm_Objections Are Sometimes Overused And Are Always Misunderstood. This Paper Will Explain The Implementations And Uses And Provide Some Alternative Solutions That Are Easier To Understand, Simpler To Use, And Work Transparently."
