Aimee Sutton, Imperas Software Ltd.
As RISC-V has shifted responsibility for processor verification to a wider community of developers, the tools, techniques, and best practices surrounding it are constantly evolving. One of these best practices is the RISC-V Verification Interface [1], or RVVI. An open standard available under Apache license on GitHub, RVVI enables reuse and efficiency in processor RTL verification by formalizing the interfaces that all RISC-V CPU testbenches should contain.
RVVI has developed and matured over time through use in a number of projects, including commercial and open-source RISC-V cores. Until recently the focus of RVVI was the verification of a single RISC-V core. However, there are several scenarios where it makes sense to extend the processor testbench to include other components. One of these scenarios is the verification of a Debug Module. Rather than create a behavioural model of the processor in order to verify the Debug Module, it makes sense to use the processor RTL to respond to Debug Mode events, so long as there is a reference model ensuring that the processor’s response is correct.
This paper will present an overview of the RVVI and explain how it facilitates processor verification. The challenges of Debug Mode co-simulation will be explained in detail, followed by an explanation of the proposed changes to RVVI. Examples based on the customer’s use case will be presented along with preliminary results from simulations run using the proposed RVVI changes. Lastly, areas for future development will be identified.
Note: the customer mentioned in this abstract will obtain approval to make their name public and participate as a co-author if the abstract is accepted.
