1137: UVM Testbench Automation for AMS Designs

In the world of design verification for Analog and Mixed Signal (AMS) SOC’s there are many problems, some of which are now relatively solved. For smaller digital blocks where C or TLM models exist as the reference specification, this specification will drive the development of a UVM bench for the block level design. However, for the equivalent level in the mixed signal design comprising several circuits working together: an RF synthesizer, radio receiver or transmitter chain, or even one entire radio transceiver with many digital controls but little digital content, no simple and standard way of quickly creating a verification bench exists. This is where there is a convergence of a lot of activity -- the work of the system designer, the work of the analog lead, the creation of the top-level schematic, and the work of the designers. All of the people involved need to start working together, and it is exactly for this reason that this is the place where there is often difficulty and a source for errors. It is also where circuit simulation is needed and becomes slow and often infeasible. This is the area that we will address. First we address the handling of analog ports in a UVM environment. Next, we address the handling of register based controls. Thirdly, we demonstrate a way to use Python and Jinja templates to construct DUT specific testbenches from the DUT port list. Finally, we show how to use UVM to manage the testing with sequences, including sequences that depend on feedback from the design. To conclude, we will present the cost (development time) and benefit (TB build time difference) when adopting this methodology.