Mike Walsh, Siemens EDA; Jin Hou, Siemens EDA
Abstract-Integration of multiple ICs in a single package is critical for high performance computing. Due to the huge number of connections after packaging the ICs, it is hard to verify the correctness of the connections. The traditional way to verify the connections requires a lot of manpower and time and is either not exhaustive or too late in the process. This paper will introduce a new way to verify the packaging connectivity using formal verification that can exhaustively verify all interconnections between the IC blocks. The flow is automatic for all steps from creating connectivity spec to verify packaging output connectivity. The automatic parallel algorithms on compute grid can verify huge numbers of connections in minutes even seconds. The script for the flow is simple and only takes a few minutes to setup. Once the script is ready, it can be reused for different packaging projects.
