1156: SV_LUT: A SystemVerilog Look Up Table package for developing complex AMS Real Number Modeling

Modern Mixed Signal System on Chip (SoC) requires tight integration between analog and digital domains. Through pre-silicon verification of analog and digital sub-systems in block and SoC level is a must for ensuring first working silicon. Unlike digital circuits, analog circuits do not have a standard verification methodology yet [1-3]. Usually in verification environment the spice based analog circuits are replaced with faster event driven behavioral models developed using VerilogAMS or SystemVerilog. In recent years SystemVerilog based Real Number Modeling (SV-RNM) and SystemVerilog User Defined Nettype (SV-UDN) is gaining popularity due to easier integration with Universal Verification Methodology (UVM) testbench [3]. Pre-computed Look Up Tables (LUT) is widely used to model the behavior of complex analog circuits. These LUTs are usually populated using data from external source like MATLAB. Unlike VerilogAMS, which has a built-in function named $table_model() [4] to support LUT by importing data from .tbl file; SystemVerilog does not have any built-in support for such functionality. This paper demonstrates a SystemVerilog package named sv_lut_pkg based mechanism for LUT table creation, population and fetch values using parameterized SystemVerilog macros. The capabilities of sv_lut_pkg package is exhibited by developing a LUT based PTAT core model using SV-RNM flow.