1160: DV UVM Based AMS Co-Simulation and Verification Methodology for Mixed Signal Designs

The paper proceeds to offer an architectural overview of the new MSV verification methodology, supporting Digital Mixed Signal (DMS) and AMS Co-simulation (Co-Sim), alongside guiding principles and implementation details. It explains the approach for dynamically switching SV real number models (RNMs) and SPICE netlists in regression runs, outlines the randomized nature of SV stimulus, and explores the Analog response. To facilitate the reuse of legacy testbenches, details of DMS checkers and assertions instantiated in Co-Sim are provided. In conclusion, the paper provides a forward-looking roadmap for the new approach. This includes the integration of the AMS sub-system's testbench into the SoC environment and the seamless incorporation of advanced features at the SoC level. Additionally, it emphasizes the adaptability of this environment, enabling multiple projects to harness the same MSV flow, thereby potentially facilitating the widespread adoption of a unified Mixed-Signal methodology.